NBSG53A: 2.5 V / 3.3 V Selectable Differential Clock / Data D Flip-Flop / Clock Divider with Reset and OLS

具体说明: The NBSG53A is a multi-function differential D fli...
  • The NBSG53A is a multi-function differential D flip-flop (DFF) or fixed divide by 2 (DIV/2) clock generator. This is part of the GigaComm family of high performance Silicon Germanium products. A strappable control pin is provided to select between the two functions. The device is housed in a low profile 4x4 mm 16-pin Flip-Chip BGA (FCBGA) package.

    The NBSG53A is a device with data, clock, OLS, reset, and select inputs. Differential inputs incorporate internal 50-ohm termination resistors and accept NECL (Negative ECL), PECL (Positive ECL), CMOS, CML, or LVDS. The OLS input is used to program the peak-to-peak output amplitude between 0 and 800 mV in five discrete steps. The RESET and SELECT inputs are single-ended and can be driven with either LVECL or LVCMOS input levels.

    Data is transferred to the outputs on the positive edge of the clock. The differential clock inputs of the NBSG53A allow the device to also be used as a negative edge triggered device.
  • 特性
  • Maximum Input Clock Frequency (DFF) > 8 GHz Typical
  • Maximum Input Clock Frequency (DIV/2) > 10 GHz Typical
  • 210 ps Typical Propagation Delay (OLS = FLOAT)
  • 45 ps Typical Rise and Fall Times (OLS = FLOAT)
  • Selectable Output Level (0 V, 200 mV, 400 mV, 600 mV, or 800 mV Peak-to-Peak Output)
  • 50 Ω Internal Input Termination Resistors on all Differential Input
  • DIV/2 Mode (Active with Select Low)
  • D Flip Flop Mode (Active with Select High)
  • Selectable Swing PECL Output with Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V
  • Selectable Swing NECL Output with NECL Inputs with Operating Range: VCC = 0 V with VEE = -2.375 V to -3.465 V
  • 应用
  • High Performance Logic for ATE and Networking
  • 终端产品
  • ATE Instrumentation, Networking
  • 技术文档及设计资源
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    供货情况和样品
    NBSG53AMNG
  • 状况: Active
  • Compliance: Pb-free Halide free 
  • 具体说明: 2.5 V / 3.3 V Selectable Differential Clock / Data D Flip-Flop / Clock Divider with Reset and OLS
  • 封装 类型: QFN-16
  • 封装 外形: 485G-01
  • MSL: 1
  • 容器 类型: TUBE
  • 容器 数量: 123
  • 库存

  • Market Leadtime (weeks):2 to 4
  • Arrow:0
  • Avnet:<1K
  • Digikey:<1K
  • Newark:<100
  • ON Semiconductor:246
  • PandS:<100
  • NBSG53AMNHTBG
  • 状况: Active
  • Compliance: Pb-free Halide free 
  • 具体说明: 2.5 V / 3.3 V Selectable Differential Clock / Data D Flip-Flop / Clock Divider with Reset and OLS
  • 封装 类型: QFN-16
  • 封装 外形: 485G-01
  • MSL: 1
  • 容器 类型: REEL
  • 容器 数量: 100
  • 库存

  • Market Leadtime (weeks):2 to 4
  • Arrow:0
  • ON Semiconductor:1,000
  • 封装
    Specifications
  • Type: D-Type 
  • Bits:
  • Input Level: CMOS  CML  LVDS  ECL 
  • Output Level: ECL 
  • VCC Typ (V): 2.5  3.3 
  • tJitter Typ (ps): 0.5 
  • tpd Typ (ns): 0.215 
  • tsu Min (ns): 0.03 
  • th Min (ns): 0.025 
  • trec Typ (ns): 0.012 
  • tR & tF Max (ps): 65 
  • fToggle Typ (MHz): 10000 
  • Package Type: QFN-16 
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