# Physical Configuration

The RSL15 system includes physical configuration parameters for each GPIO. These parameters are set using configuration bits from the appropriate GPIO_CFG_* registers.

If the GPIO is configured as an input pad, the GPIO_CFG_PULL_CTRL bit field is used to configure the pad to use a pull-up or pull-down resistor. Options include:

- No pull resistor
- A weak (250 kΩ) pull-up resistor
- A weak (250 kΩ) pull-down resistor
- A strong (10 kΩ) pull-up resistor

In the reset state — for example, when the NRESET pad is driven low — the GPIO output drive is disabled and a weak (250 kΩ) pull-up resistor is enabled. After reset is released, the default GPIO configuration is applied.

The GPIO_CFG_LPF bits in the GPIO_CFG registers enables or disables a low-pass filter that can be used to provide a cleaner input signal by filtering out high frequency noise.

IMPORTANT: For optimal noise performance, we recommend enabling the low-pass filters provided for GPIO inputs when using input signals received at 1 MHz or less. For signals that use a frequency exceeding 1 MHz, the GPIO low-pass filters need to be disabled.

NOTE: When switching from disabled to GPIO output mode:

- From an input mode, the initial output value matches the value that has most recently been read from the input.
- From another output mode, the initial output value matches the current output value.
- The initial output value matches the value shown in the GPIO_OUTPUT_DATA register.

IMPORTANT: When a GPIO is configured as output, its value is based on its previous GPIO data register. Therefore, before configuring a GPIO to produce a specific output level, the application must set the GPIO register first and then configure the GPIO as an output.

If the GPIO is configured as an output pad, the GPIO_CFG_DRIVE bit allows you to select the drive strength for the GPIO output, with settings for 2x, 3x, 5x, and 6x the normal drive strength.

## nRESET Pull Resistor Configuration

In the reset state, the nRESET signal has a 100 kΩ pull-up resistor. When the ACS is not in reset, the nRESET signal has a 200 kΩ pull-up resistor. The physical characteristics for the nRESET pad are not otherwise configurable.

## JTAG I/O Pad Configuration

Physical configuration of the JTAG TDO, TDI, and TRSET signals are as per their corresponding GPIO physical configuration. The dedicated SWJ-DP pads, used as the SWCLK (JTAG JTCK) and SWDIO (JTAG JTMS) have separate physical configurations, controlled by the GPIO_JTAG_SW_PAD_CFG register. This includes:

- The GPIO_JTAG_SW_PAD_CFG_SWCLK_PULL and GPIO_JTAG_SW_PAD_CFG_SWDIO_PULL bits are used for configuring each pad to use a pull-up or pull-down resistor. These pads have the same pull-resistor configuration options as the GPIO pads, allowing for selection of no pull resistor, a weak or strong pull-up resistor, or a weak pull-down resistor.
- The GPIO_JTAG_SW_PAD_CFG_SWCLK_LPF and GPIO_JTAG_SW_PAD_CFG_SWDIO_LPF bits are used to enable or disable the low-pass filters, which can be used to provide a cleaner input signal by filtering out high frequency noise.
- The GPIO_JTAG_SW_PAD_CFG_SWDIO_DRIVE bit is used to select the drive strength for the SWDIO output, with settings for 2x, 3x, 5x, and 6x the normal drive strength.