### I2C_CFG

Bit Field | Read/Write | Field Name | Description
--- | --- | --- | ---
30 | RW | REPEATED_START_INT_ENABLE | Configure whether repeated start interrupts will be generated by the I2C interface for active transactions in slave mode
29 | RW | CONNECT_IN_STANDBY | Control if the I2C lines are connected when running on the standby clock
28 | RW | TX_DMA_ENABLE | Enable/disable the TX DMA request
27 | RW | RX_DMA_ENABLE | Enable/disable the RX DMA request
26 | RW | TX_INT_ENABLE | Enable/disable the TX interrupt
25 | RW | RX_INT_ENABLE | Enable/disable the RX interrupt
24 | RW | BUS_ERROR_INT_ENABLE | Enable/disable the bus error interrupt
23 | RW | OVERRUN_INT_ENABLE | Enable/disable the overrun interrupt
22 | RW | STOP_INT_ENABLE | Configure whether stop interrupts will be generated by the I2C interface
21 | RW | AUTO_ACK_ENABLE | Select whether acknowledgement is automatically generated or not
20:16 | RW | SLAVE_PRESCALE | Controls the number of SYSCLK wait cycles in case of clock streching (in slave mode) between the moment the data is put on the SDA line and the SCL line is released.
15:8 | RW | MASTER_PRESCALE | Prescaler used to divide SYSCLK to the correct SCL frequency when operating in master mode. SCL is prescaled by (PRESCALE + 1) * 3.
7:1 | RW | SLAVE_ADDRESS | Set the I2C slave address for this device
0 | RW | SLAVE | Select whether the I2C interface is enabled for slave mode or not

Bit Field | Field Name | Value Symbol | Value Description | Hex Value
--- | --- | --- | --- | ---
30 | REPEATED_START_INT_ENABLE | I2C_REPEATED_START_INT_DISABLE | Repeated start interrupts are not generated | 0x0*
|  | I2C_REPEATED_START_INT_ENABLE | A repeated start interrupt is generated when a repeated start condition occurs during an active transaction in slave mode | 0x1
29 | CONNECT_IN_STANDBY | I2C_DISCONNECT_IN_STANDBY | Disconnect the I2C lines when running on standby clock | 0x0*
|  | I2C_CONNECT_IN_STANDBY | Keep the I2C lines connected when running on standby clock | 0x1
28 | TX_DMA_ENABLE | I2C_TX_DMA_DISABLE | No TX DMA request is generated | 0x0*
|  | I2C_TX_DMA_ENABLE | A TX DMA request is generated when new data is requested by the I2C interface | 0x1
27 | RX_DMA_ENABLE | I2C_RX_DMA_DISABLE | No RX DMA request is generated | 0x0*
|  | I2C_RX_DMA_ENABLE | An RX DMA request is generated when new data is received by the I2C interface | 0x1
26 | TX_INT_ENABLE | I2C_TX_INT_DISABLE | No TX interrupt is raised | 0x0*
|  | I2C_TX_INT_ENABLE | A TX interrupt is raised when new data is requested by the I2C interface | 0x1
25 | RX_INT_ENABLE | I2C_RX_INT_DISABLE | No RX interrupt is raised | 0x0*
|  | I2C_RX_INT_ENABLE | An RX interrupt is raised when new data is received by the I2C interface | 0x1
24 | BUS_ERROR_INT_ENABLE | I2C_BUS_ERROR_INT_DISABLE | No bus error interrupt is raised when an overrun is detected | 0x0*
|  | I2C_BUS_ERROR_INT_ENABLE | A bus error interrupt is raised when an overrun occurs on the I2C interface | 0x1
23 | OVERRUN_INT_ENABLE | I2C_OVERRUN_INT_DISABLE | No overrun interrupt is raised when an overrun is detected | 0x0*
|  | I2C_OVERRUN_INT_ENABLE | An overrun interrupt is raised when an overrun occurs on the I2C interface | 0x1
22 | STOP_INT_ENABLE | I2C_STOP_INT_DISABLE | Stop interrupts are not generated | 0x0*
|  | I2C_STOP_INT_ENABLE | A stop interrupt is generated when a stop condition occurs for an active transaction | 0x1
21 | AUTO_ACK_ENABLE | I2C_AUTO_ACK_DISABLE | Require manual acknowledgement of all I2C interface transfers | 0x0*
|  | I2C_AUTO_ACK_ENABLE | Use automatic acknowledgement for I2C interface transfers | 0x1
20:16 | SLAVE_PRESCALE | I2C_SLAVE_PRESCALE_1 | Slave Standard-mode: at least 250 ns +10% data set-up time with SYSCLK = 3 MHz; Slave Fast-mode: at least 100 ns +10% data set-up time with SYSCLK = 3, 4, 5, 8 MHz; Slave Fast-mode Plus: at least 50 ns +10% data set-up time with SYSCLK = 3, 4, 5, 8, 10, 12, 16 MHz | 0x0*
|  | I2C_SLAVE_PRESCALE_2 | Slave Standard-Mode: at least 250 ns +10% data set-up time with SYSCLK = 4, 5 MHz; Slave Fast-Mode: at least 100 ns +10% data set-up time with SYSCLK = 10, 12, 16 MHz; Slave Fast-mode Plus: at least 50 ns +10% data set-up time with SYSCLK = 20, 24 MHz | 0x1
|  | I2C_SLAVE_PRESCALE_3 | Slave Standard-Mode: at least 250 ns +10% data set-up time with SYSCLK = 8, 10 MHz; Slave Fast-Mode: at least 100 ns +10% data set-up time with SYSCLK = 20, 24 MHz; Slave Fast-mode Plus: at least 50 ns +10% data set-up time with SYSCLK = 48 MHz | 0x2
|  | I2C_SLAVE_PRESCALE_4 | Slave Standard-Mode: at least 250 ns +10% data set-up time with SYSCLK = 12 MHz | 0x3
|  | I2C_SLAVE_PRESCALE_5 | Slave Standard-Mode: at least 250 ns +10% data set-up time with SYSCLK = 16 MHz | 0x4
|  | I2C_SLAVE_PRESCALE_6 | Slave Standard-Mode: at least 250 ns +10% data set-up time with SYSCLK = 20 MHz; Slave Fast-Mode: at least 100 ns +10% data set-up time with SYSCLK = 48 MHz | 0x5
|  | I2C_SLAVE_PRESCALE_7 | Slave Standard-Mode: at least 250 ns +10% data set-up time with SYSCLK = 24 MHz | 0x6
|  | I2C_SLAVE_PRESCALE_14 | Slave Standard-Mode: at least 250 ns +10% data set-up time with SYSCLK = 48 MHz | 0xD
|  | I2C_SLAVE_PRESCALE_32 | Maximum number of clock stretching cycles between SDA output and SCL release | 0x1F
15:8 | MASTER_PRESCALE | I2C_MASTER_PRESCALE_3 | Master mode: prescale SCL from SYSCLK by 3 | 0x0*
|  | I2C_MASTER_PRESCALE_6 | Master mode: prescale SCL from SYSCLK by 6 | 0x1
|  | I2C_MASTER_PRESCALE_9 | Master mode: prescale SCL from SYSCLK by 9 | 0x2
|  | I2C_MASTER_PRESCALE_12 | Master mode: prescale SCL from SYSCLK by 12 | 0x3
|  | I2C_MASTER_PRESCALE_15 | Master mode: prescale SCL from SYSCLK by 15 | 0x4
|  | I2C_MASTER_PRESCALE_18 | Master mode: prescale SCL from SYSCLK by 18 | 0x5
|  | I2C_MASTER_PRESCALE_21 | Master mode: prescale SCL from SYSCLK by 21 | 0x6
|  | I2C_MASTER_PRESCALE_24 | Master mode: prescale SCL from SYSCLK by 24 | 0x7
|  | I2C_MASTER_PRESCALE_27 | Master mode: prescale SCL from SYSCLK by 27 | 0x8
|  | I2C_MASTER_PRESCALE_30 | Master mode: prescale SCL from SYSCLK by 30 | 0x9
|  | I2C_MASTER_PRESCALE_33 | Master mode: prescale SCL from SYSCLK by 33 | 0xA
|  | I2C_MASTER_PRESCALE_36 | Master mode: prescale SCL from SYSCLK by 36 | 0xB
|  | I2C_MASTER_PRESCALE_39 | Master mode: prescale SCL from SYSCLK by 39 | 0xC
|  | I2C_MASTER_PRESCALE_42 | Master mode: prescale SCL from SYSCLK by 42 | 0xD
|  | I2C_MASTER_PRESCALE_45 | Master mode: prescale SCL from SYSCLK by 45 | 0xE
|  | I2C_MASTER_PRESCALE_48 | Master mode: prescale SCL from SYSCLK by 48 | 0xF
|  | I2C_MASTER_PRESCALE_51 | Master mode: prescale SCL from SYSCLK by 51 | 0x10
|  | I2C_MASTER_PRESCALE_54 | Master mode: prescale SCL from SYSCLK by 54 | 0x11
|  | I2C_MASTER_PRESCALE_57 | Master mode: prescale SCL from SYSCLK by 57 | 0x12
|  | I2C_MASTER_PRESCALE_60 | Master mode: prescale SCL from SYSCLK by 60 | 0x13
|  | I2C_MASTER_PRESCALE_120 | Master mode: prescale SCL from SYSCLK by 120 | 0x27
|  | I2C_MASTER_PRESCALE_768 | Master mode: prescale SCL from SYSCLK by 768 | 0xFF
0 | SLAVE | I2C_SLAVE_DISABLE | Disable I2C interface slave mode operation | 0x0*
|  | I2C_SLAVE_ENABLE | Enable I2C interface slave mode operation | 0x1