# RFFE System Resources

An overall and simplified digital diagram of the RFFE is shown in the "Simplified Digital Schematic Diagram" figure.

Figure: Simplified Digital Schematic Diagram

The required clocks are generated from the RFCLK.

Other key RFFE elements include:

FSM

This block contains the finite state machine (FSM) that controls the transceiver status. The FSM block provides the dynamic configuration to turn on the analog blocks, for sending or receiving data or packets.

BB clk gen block

This block generates the required clocks for the digital baseband (CK_BIT, CK_SYM, CK_OS, CK_FE, CK_TX). It also provides the signals for the clock generation of the analog blocks that require it (phADC and channel filter).

TX and RX FIFO

These blocks are a 128-byte FIFO. The TX FIFO receives data from the interface (APB or SPI) and sends it to the TX when requested. The RX FIFO receives data from the RX and sends it to the interface when requested.

TX

This block handles the TX process and it is composed of three sub-blocks: the serializer, the coder, and the modulator. The serializer takes the data from the TX FIFO and sends it to the coder in the order specified by the packet format. The coder takes these data and encodes them (Manchester, IEEE 802.15.4, etc.) Finally, the modulator processes the encoded data to be sent to the PLL for direct modulation.

RX

This block is the digital receiver of the system. It is composed of three sub-blocks: the demodulator, the decoder, and the deserializer. The demodulator takes the data from the phADC and the RSSI, and performs many operations: carrier recovery, matched filtering, clock recovery, RSSI averaging, ISI corrections, etc. The output is fed to the decoder, which is able to decode several types of encoding. Once decoded, the data is sent to the deserializer, which handles the packet format and fills the RX FIFO.

## 48 MHz Crystal Oscillator

As has been indicated, a 48 MHz clock is required for the RFFE to work as expected with clock accuracy conforming to the technology’s standard specification. This clock is is generated using a 48 MHz crystal oscillator connected to the RSL15 XTAL pins, and is routed directly to the RFFE (independent of the RFCLK configuration). For more information, see Clock Generation.

For Bluetooth Low Energy, the clock accuracy must be better than 50 ppm during data transmission or reception.

The 48 MHz crystal oscillator can be trimmed through the RF_REG2E_XTAL_TRIM_XTAL_TRIM field of register RF_REG2E. Once it is written, it starts an algorithms that trims the 48 MHz frequency. This trim bit field is divided into 5 MSBs that provide coarse trimming, and 3 LSBs for fine trimming. The end of the trimming algorithm can be checked by reading the RF_ANALOG_INFO_ANALOG_INFO_XTAL_FINISH bit of the RF_ANALOG_INFO register.

This algorithm can be bypassed by setting the RF_XTAL_CTRL_XTAL_CTRL_XTAL_CTRL_BYPASS bit of the RF_XTAL_CTRL register to 1.

The XTAL_TRIM for a specific crystal can be calibrated by outputting a divided RF clock and trimming that clock to the expected division of 48 MHz. Trim settings on RSL15 are expected to be consistent for a population of crystals showing similar impedance characteristics.

NOTE: Custom calibration settings for XTAL_TRIM can be stored to NVR6, as described in the RSL15 Firmware Reference Manual Resource Usage table. If available, these values are loaded by the sample code provided in the SDK.

## Radio Clocks

RFFE needs several clocks to work correctly:

- CK_OS: an oversampled clock compared to the symbol rate. Golden rule: the oversampling ratio is 8.
- CK_SYM: the symbol clock. This clock has the same frequency as the symbol rate.
- CK_BIT: the bit clock. This clock has the same frequency as the bit rate. If there is 1 bit/symbol, CK_BIT and CK_SYM have the same frequency; in case of 2 bits/symbol, CK_BIT has a frequency two times higher than the CK_SYM. This clock is generated by the coding blocks.
- CK_TX: this is the clock that is used in the TX interpolator. Basically the output to the PLL is clocked at this frequency.
- CK_FRONTEND: this is the clock that is used in the RX frontend processor. It is the same clock as the phADC. The RSSI has another clock but it can be programmed to use the same clock as the phADC.
- CK_FILTER: this clock is used by the channel filter in order to tune the center frequency and the bandwidth.

The frequencies of the clocks are specified by an integer value. The frequency is given by the system frequency divided by this value increased by 1. So a value of 3, when the system frequency is set to 16 MHz, gives 16 MHz/(3+1) = 4 MHz.

The CK_OS, CK_BIT, and CK_SYM clocks are controlled by the RF_REG08_MOD_INFO_*_DR_M_*[4:0] and RF_REG0_MOD_INFO_*_SYMBOL_2BIT_* fields of the RF_REG08 register. The former field specifies the oversampling frequency CK_OS. The CK_TX is controlled by the RF_REG01_MOD_TX_CK_TX_M[4:0] field of the RF_REG01 register. The CK_FRONTEND clock for the phADC is controlled by the RF_FRONTEND_FRONTEND_DIV_PHADC[3:0] field of the RF_FRONTEND register. The RSSI clock is controlled by RF_REG01B_ANACLK_DIV_RSSI[3:0] field of the RF_REG1B register. Alternatively, the RSSI can use the same clock as the phADC by setting the RF_REG2D_RSSI_TUN_2_RSSI_ONE_CK_RSSI_PHADC field of the RF_REG2D register. Finally, the CK_FILTER clock is controlled by the RF_REG1B_ANACLK_DIV_FILT[3:0] field of the RF_REG1B register. The CK_FILTER and CK_FRONTEND clocks are also fed to the analog blocks.

## Registers

There are two kinds of registers used for the RF front-end: static registers, and dynamic registers. The static registers are used to configure the so-called static configuration of the transceiver. The dynamic registers are inside blocks that are working with the RFFE system clock. Accessing these two types of register is carried out in the same way for each type, and is transparent to the user except for the fact that the clock has to be enabled in the digital blocks. To activate this clock, the RF_REG00_MODE_MODE[1:0] field of the RF_REG00 register has to be set to 10.

The RFFE has two banks of registers that contain the essential configuration needed to change modulation parameters on the fly. The registers that are banked are noted as "banked" in the register list. The register bank can be chosen with the RF_REG08_BANK_BANK[0:1] field of the RF_REG08 register (using the RF0_REG notation). Bank 0 registers can be accessed directly using RF1_REG notation, while the bank 1 registers can be accessed directly using RF2_REG notation. To provide a more flexible configuration, the configuration bits that are common to TX and RX have been split into two registers. These configuration bits are RF_REG08_MOD_INFO_*_DIV_CK_*, RF_REG08_MOD_INFO_*_SYMBOL_2BIT_*, and RF_REG08_MOD_INFO_*_DR_M_*[4:0], all from the RF_REG08 register. The value to use is specified by the RF_REG08_BANK_DATARATE_TX_NRX field of the RF_REG08 register.

The Bluetooth 5 standard specifies 4 data-rates: 1 Mbps, 2 Mbps, coded 125 kbps, and coded 500 kbps. The two coded data-rates used the 1Mbps modulation schemes and simply add a coding stage to the bitstream. RFFE is capable of supporting these 4 data-rates by configuring only the 1 Mbps and 2 Mbps rates. In this case, bank 0 needs to be loaded with the 1 Mbps configuration and all the parameters for the coded rates correctly set (except for the enable bits), and bank 1 with the 2 Mbps rate. The RF_REG08_BANK_STD_BLE_RATES bit of the RF_REG08 register need to be set to 1. At this point, selecting bank 2 corresponds to the coded 125 kbps data rate, and bank 3 corresponds to the 500 kbps data rate. Note that this is only valid for the TX; in RX mode, the packet rate indicator shows the data rate. So, in RX, the behaviors of bank 2 and 3 are the same.

## FSM and Global Configuration

The behavior of the digital baseband radio is determined by the values in the following fields of the RF_REG00 register:

- RF_REG00_MODE_MODE: select the working mode of the digital baseband.
  - 00: the digital baseband is off (no clock).
  - 01: the clock is generated but the blocks are reset (TX, RX, FIFOs, and finite state machine (FSM)).
  - 10: the digital baseband is frozen.
  - 11: working
- RF_REG00_MODE_TX_NRX: if set to 1, it uses TX, otherwise RX.
- RF_REG00_MODE_EN_SERIALIZER: if set to 1, enables the serializer.
- RF_REG00_MODE_EN_DESERIALIZER: if set to 1, enables the deserializer.
- RF_REG00_MODE_EN_FSM: if set to 1, enables the radio FSM.
- RF_REG00_MODE_NOT_TO_IDLE: in FSM Mode, if set to 1, indicates to the FSM to go into Suspend Mode after a TX or RX packet.
- RF_REG00_MODE2_TESTMODE: set the output Test Mode.
- RF_REG00_MODE2_PSK_NFSK: if set to 1, the PSK Mode is selected; FSK is selected otherwise.
- RF_REG00_MODE2_DIFF_CODING: if set to 1, enables the differential coding/decoding.

RF_REG00_MODE_MODE[1:0] is the most important in the above list, as it determines the status of the digital baseband. RX or TX mode is determined by the RF_REG00_MODE_TX_NRX field; note that this is overridden when the system is in FSM Mode. The serializer and the deserializer can be activated with the RF_REG00_MODE_EN_DESERIALIZER and RF_REG00_MODE_EN_SERIALIZER fields. However, the most suitable working mode is the FSM Mode.

The modulation scheme can be chosen using the RF_REG00_MODE2_PSK_NFSK field of the RF_REG00 register. However, this is applied only on the RX side, with some limitations: for PSK modulation, only O-QPSK modulation is supported.

The radio is activated by setting bit 0, which is the RF_FSM_CTRL_FSM_MODE_MODE field of the RF_FSM_CTRL register, to 1. The FSM then activates the TX or the RX, depending on the value of bit 2, the RF_FSM_CTRL_FSM_MODE_TX_NRX bit of the same register. The sub-band algorithm can be activated at the same time, by setting bit 1, the RF_FSM_CTRL_FSM_MODE_TX_MODE bit of the same register, to 1. The calibration is performed before the packet’s transmission/reception. Finally, the FSM can be reset at any time by setting the RF_FSM_CTRL_FSM_MODE_RESET bit in the same register to 1.

When FSM is enabled and set to start TX or RX, it uses some internal timers to enable different blocks required for TX or RX. For TX, sub-blocks PLL, DLL, DIG RF, and RF TX (analog) are turned on. For RX, sub-blocks PLL, RF RX, and DIG RX are on. The transitional states have to be maintained for the right amount of time, to avoid such problems as sending a message when the PLL is not yet stabilized. The time needed by each category of blocks can be specified in the RF_AGC_ATT2_TIMINGS_* fields of the RF_AGC_ATT2 register, and the RF_REG25_TIMINGS_* fields of the RF_REG25 register. The timings of the categories are specified by an integer value. The corresponding time is given by this value increased by 1 and multiplied by the time granularity. This is specified by the RF_AGC_ATT2_TIMINGS_1_T_GRANULARITY_TX[3:0] and RF_AGC_ATT2_TIMINGS_1_T_GRANULARITY_RX[3:0] fields of the RF_AGC_ATT2 registers. The time granularity is given by:

The timings can range from 0.25 μs to 262.1 ms, a range that is generally large enough. In the case of sub-band selection during startup, the sequence is slightly modified: since the PLL and/or the DLL need to run during sub-band selection, the activation time of these two blocks is modified in order for them to wake up before the beginning of the algorithm. In practice, the activation time of the sub-band selection algorithm is added to the activation time of the PLL and DLL.

### TX and RX Start Sequence Example

To explain how long TX and RX are on from the time The RF_FSM_CTRL_FSM_MODE_* bits of the RF_FSM_CTRL register are written, two examples are provided.

- TX Example: A system is configured with the following bit field values of the RF_AGC_ATT2 register:

RF_AGC_ATT2_TIMINGS_1_T_GRANULARITY_TX = 2

RF_AGC_ATT2_TIMINGS_2_T_SUBBAND_TX = 4

RF_AGC_ATT2_TIMINGS_2_T_TX_RF = 0

RF_AGC_ATT2_TIMINGS_3_T_DLL = 4

RF_AGC_ATT2_TIMINGS_3_T_PLL_TX = 2

If the FSM is activated with the activate TX only command—that is to say, without performing sub-band selection — during the startup sequence of the TX, the FSM timer is set to 4; this is the maximum value between RF_AGC_ATT2_TIMINGS_2_t_tx_rf, RF_AGC_ATT2_TIMINGS_2_t_pll_tx, and RF_AGC_ATT2_TIMINGS_2_t_dll. This timer decreases every 1 μs. If the sub-band selection is performed during the activation, the RF_AGC_ATT2_TIMINGS_2_t_pll_tx and RF_AGC_ATT2_TIMINGS_2_t_dll values are increased by the value of RF_AGC_ATT2_TIMINGS_2_t_subband_tx. As a result, the internal timer starts at the value of 8, which is the maximum value between RF_AGC_ATT2_TIMINGS_2_t_pll + RF_AGC_ATT2_TIMINGS_2_t_subband_tx, RF_AGC_ATT2_TIMINGS_2_t_dll + RF_AGC_ATT2_TIMINGS_2_t_subband_tx, and RF_AGC_ATT2_TIMINGS_2_t_tx_rf. All variables are fields in the RF_AGC_ATT2_TIMINGS_2 register.

- RX Example: A system is configured with the following bit field values:

RF_AGC_ATT2_TIMINGS_1_T_GRANULARITY_RX in register RF_AGC_ATT2 = 0x4

RF_REG25_TIMINGS_4_T_PLL_RX in register RF_REG25 = 0x4

RF_REG25_TIMINGS_5_T_RX_RF = 0x1

RF_REG25_TIMINGS_5_T_RX_BB = 0x4

The granularity is 4 μs, meaning that the internal timer changes every 4 μs. In this case the maximum value is 4, so the internal timer is set to 4. Note that since the granularity of the counter is 4, the whole sequence takes 20 μs. Also note that this is only the power-up sequence for the RX; if the required data is at the antenna at the exact moment of the rising edge of the digital enable signal, that data is available only after the RX processing delay. Sub-band selection is activated, the behavior is similar to the TX case; the sub-band time is added to the PLL power-up time only.

### RX Timeout

The RX timeout can be enabled by setting the RF_REG25_TIMEOUT_EN_RX_TIMEOUT bit of the RF_REG25 register to 1. The length of the timeout can be specified by the RF_REG25_TIMEOUT_T_RX_TIMEOUT[3:0] and RF_REG25_TIMEOUT_T_TIMEOUT_GR[2:0] fields of the same register. The definition of granularity is the same as for the timings, except that it is 16 times larger. So the timeout range is from 16 μs to 4.2 s. If the timeout expires, the FSM stays in the RX state as long as the pattern has been received; otherwise, it switches to the Idle or SuspendRX state, depending on the configuration of RF_REG00_MODE_NOT_TO_IDLE bit of the RF_REG00 register. The timeout can be calculated using the following equation:

### MAC Timers

Modern protocols require precise and short timings between packets. In order to achieve these constraints, the RFFE provides an automatic timed re-activation of the TX or RX. For example, the RX can be activated after a packet’s transmission in readiness to receive the acknowledgment. Another example is a broadcaster node that sends a packet every 150 μs.

This function can be activated by setting to 1 the RF_REG03_MAC_CONF_RX_MAC_ACT or the RF_REG03_MAC_CONF_TX_MAC_ACT fields of the RF_REG03 register. The first enables the re-activation of the radio after an RX mode, while the second is used in a TX mode. The mode to activate is specified by the RF_REG03_MAC_CONF_RX_MAC_TX_NRX and RF_REG03_MAC_CONF_RX_MAC_TX_NRX fields of the RF_REG03 register: set to 1, the next mode is the TX mode, and set to 0, the next mode is the RX mode. The time to wait after each mode is specified by the fields RF_PADS_89_RX_MAC_TIMER_RX_MAC_TIMER and RF_PADS_89_TX_MAC_TIMER_TX_MAC_TIMER of the RF_PADS_89 register. The time base is specified by the RF_REG03_MAC_CONF_MAC_TIMER_GR[1:0] field of the RF_REG03 register, and is equal to 2(2mac_timer_gr) μs. Timer activation can be chosen using the RF_REG03_MAC_CONF_RX_MAC_START_NSTOP and RF_REG03_MAC_CONF_TX_MAC_START_NSTOP fields of the RF_REG03 register. If RF_REG03_MAC_CONF_RX_MAC_START_NSTOP is set to 0, the timer is activated at the packet end (when the RX is turned off), while if it is set to 1, the timer is activated at the sync word reception. If the RF_REG03_MAC_CONF_TX_MAC_START_NSTOP field is set to 0, the timer is activated at the end of packet transmission, while if it is set to 1, the timer is activated with the activation of packet transmission.

### Protocol Timers

The protocol timer is more complex that the MAC timers, but it offers more possibilities and flexibility. In order to enable the protocol timer, the RF_PROT_TIMER_PROT_TIMER_CONF_END_PROT_TIMER bit of the RF_PROT_TIMER register needs to be set to 1. To understand how to configure the protocol timer, several aspects of it need to be understood and programmed correctly.

### Time Stamps

The protocol timer allows your application to work with time stamp information. There are two time stamps. A time stamp is used to memorize the state of an internal timer when a particular event triggers it. The time stamps configurations are programmed through the RF_PROT_TIMER_PROT_TIMER_CONF_PT_T_STP_* fields of register RF_PROT_TIMER. The available configurations are:

- 000 No time stamp
- 001 Protocol timer trigger: a time stamp is created if a protocol timer command is sent.
- 01- Reserved for future use
- 100 TX Stop: a time stamp is created at the end of the TX phase.
- 101 RX Sync: a time stamp is created at the detection of the synchronization word.
- 110 RX Stop: a time stamp is created at the end of an RX phase (FSM radio transition from RX to Idle).
- 111 RX Received: a time stamp is created at the reception of a correct packet (no CRC errors).

### Delta Time

It is possible to specify time intervals between a time stamp and the next event that needs to be generated; these intervals are called delta time. In the actual version there are 2 delta time intervals. A delta time is programmed through the RF_PT_DELTA_0_PT_DELTA_TS_0_PT_DELTA_T0_MULT[13:0] and RF_PT_DELTA_0_PT_DELTA_TS_0_PT_DELTA_T0 [1:0] fields of the RF_PT_DELTA_0 register, and the RF_PT_DELTA_1_PT_DELTA_TS_1_PT_DELTA_T1_MULT[13:0] and RF_PT_DELTA_1_PT_DELTA_TS_1_PT_DELTA_T1 [1:0] fields of the RF_PT_DELTA_1 register. The delta time value in μs is given by the formula:

NOTE: The definition of time delta and time stamp are completely separated, i.e., there is no connection between time stamp 0 and time delta 0.

### Commands

It is possible to send a command to the protocol timer in order to schedule an event. A protocol timer command requires specifying the following points:

- An operation
- A time stamp
- A delta time
- An action

The protocol timer command is specified by the RF_REG50_PROT_TIMER_PT_CMD[7:0] field of register RF_REG50. It is composed as shown in the "Protocol Timer Command" figure:

Figure: Protocol Timer Command

The protocol timer operations are:

- 00: Add an event to be scheduled from the actual time.
- 01: Add an event to be scheduled from the time stamp specified in the command.
- 10: Add a periodic event to be scheduled from the time stamp specified in the command.
- 11: Clear all schedules.

The periodic event schedule is like a normal event schedule, except that it is renewed every time that a new time stamp is generated. So it is possible to automatically retrigger an event and reproduce a periodic behavior.

The possible actions are essentially the activation of the TX or RX, with or without sub-band selection. The MSB of the command’s Action field (as shown in Protocol Timer Command (figure)) specifies if the sub-band selection need to be performed, and the LSB specifies whether it is a TX or RX activation. In summary, the protocol timer actions are:

- 00: RX without sub-band selection
- 10: RX with sub-band selection
- 01: TX without sub-band selection
- 11: TX with sub-band selection

There are four possible parallel schedules. The internal timer has 24 bits, so its periodicity is 16.7 s. If an event scheduling is incorrectly programmed, it can happen 16 s later.

### Protocol Timer, Delta Timer, and Command Example

As the first example, a packet needs to be sent 150 μs after the reception of a packet. Time stamp 0 and delta time 0 are used. Here are the steps in the example:

- Set the RF_PROT_TIMER_PROT_TIMER_CONF_EN_PROT_TIMER field of the RF_PROT_TIMER register to 1.
- First a time stamp is set on the RX Received signal: the RF_PROT_TIMER_PROT_TIMER_CONF_PT_T_STP_0 field of the RF_PROT_TIMER register is set to “111”.
- The RF_PT_DELTA_0_PT_DELTA_TS_0_PT_DELTA_T0_MULT field of the RF_PT_DELTA_0 register = 00, since 150 μs is low enough
- For the RF_PT_DELTA_0_PT_DELTA_TS_0_PT_DELTA_T0 field in the same register, we need to know the power-up time and the RX path delay. Here we suppose 25 μs for the TX power-up and 5 μs for the RX path delay, so RF_PT_DELTA_0_PT_DELTA_TS_0_PT_DELTA_T0 = 120 = 0x78.
- Now the command can be sent with pt_cmd = 0xC1 :
  - Action = 11 : TX with subband selection
  - Delta time = 00
  - Time stamp = 00
  - Operation = 01: add to time stamp n.

In the second example, a packet needs to be sent after 1 ms and then another packet sent every 625 μs. Time stamp 0 is used for the periodic part, delta time 0 is used for the first delay of 1 ms, and delta time 1 is used for the periodic time.

- Set the RF_PROT_TIMER_PROT_TIMER_CONF_EN_PROT_TIMER field of the RF_PROT_TIMER register to 1.
- Set time-stamp 0 to be trigger by the protocol timer: the RF_PROT_TIMER_PROT_TIMER_CONF_PT_T_STP_0 field of the RF_PROT_TIMER register = 001
- RF_PT_DELTA_0_PT_DELTA_TS_0_PT_DELTA_T0_MULT = RF_PT_DELTA_1_PT_DELTA_TS_1_PT_DELTA_T1_MULT = 0
- Set the first delta time to 1 ms: the RF_PT_DELTA_0_PT_DELTA_TS_0_PT_DELTA_T0 field in the RF_PT_DELTA_0 register = 0x3E8
- Set the second delta time to 625 μs: the RF_PT_DELTA_1_PT_DELTA_TS_1_PT_DELTA_T1 in the RF_PT_DELTA_1 register = 0x271
- Send a first schedule for the first packet: pt_cmd = 0xC0
  - Action = 11 : TX with subband selection
  - Delta time = 00
  - Time stamp = 00
  - Operation = 00: add to actual time.
- Then set the periodic timer. This operation is ideally performed after the first transmission, since a packet can be triggered in between due to the periodicity of the internal counter. For the periodic packet pt_cmd = 0xD2:
  - Action = 11 : TX with subband selection
  - Delta time = 01
  - Time stamp = 00
  - Operation = 10: add periodic event to time stamp n.

## RFFE GPIO

The RFFE has 10 GPIOs that can be configured to assist in monitoring IRQs and other signals while debugging protocol implementations that use the RFFE. The configuration of the GPIOs is specified by the RF_PADS_03, PAD_CONF_5 , and RF_PADS_89 registers, through their RF_PADS_*PAD_CONF*_PAD_*_CONF fields. The values of these fields are associated with the following functions, as shown in the "RFFE GPIO Configuration" figure:

Figure: RFFE GPIO Configuration

When Test Mode (0x0F) is selected, the meaning and purpose of signals associated with the configured GPIO and the direction of the GPIO depends on the Test Mode number written in the RF_REG00_MODE2_TESTMODE field of register RF_REG00. Test Mode options are shown in the "Testbus Modes" figure:

Figure: Testbus Modes

The RSL15 Bluetooth stack communicates with the RFFE through dedicated hardware that sends and receives data and clocks in Test Mode equal to 0x08. To enable FSM and start TX or RX, it uses an internal SPI to communicate to the RFFE SPI for control purposes.

To route an RFFE GPIO, in addition configuring the desired GPIO in RFFE, one of the RSL15 GPIOs needs to be configured so that the system GPIO multiplexer can connect the RFFE GPIO to the SoC GPIO. For example, the following code can configue GPIO10 of RSL15 to route the RFFE TX active signal through connecting RFFE GPIO#5 to RSL15 GPIO10:

RF0_PADS_47->PAD_CONF_2_PAD_5_CONF_BYTE = 0x16;

SYS_GPIO_CONFIG(10, (GPIO_6X_DRIVE | GPIO_LPF_DISABLE | GPIO_WEAK_PULL_UP | GPIO_MODE_RF_GPIO5));

## Interrupts

The RFFE has six IRQs that can be used to increase the usability of the chip. These are defined below:

RF_TX_IRQ

Interrupt is raised at the end of a packet transmission. The IRQ is cleared by reading the RF_IRQ_STATUS register.

RF_RXSTOP_IRQ

Interrupt is raised when the FSM stops the RX Mode, independently of whether a packet has been received or not. The IRQ is cleared by reading the RF_IRQ_STATUS or RF_DESER_STATUS registers.

RF_IRQ_RECEIVED_IRQ

Interrupt is raised when a packet is received and stored in the FIFO. The IRQ is cleared by reading the RF_IRQ_STATUS or the RF_DESER_STATUS register.

RF_SYNC_IRQ

Interrupt is raised when the sync word is detected in RX Mode. The IRQ is cleared by reading the RF_IRQ_STATUS or the RF_DESER_STATUS register.

RF_TXFIFO_IRQ

Interrupt is raised when the RF_FSM_CTRL_TXFIFO_STATUS_TXFIFO_NEAR_UNDERFLOW bit from the RF_FSM_CTRL register is high. Since the IRQ is tied to the near underflow flag of the FIFO, it can be cleared by filling the FIFO with enough data.

RF_RXFIFO_IRQ

Interrupt is raised when the RF_FSM_CTRL_RXFIFO_STATUS_RXFIFO_NEAR_OVERFLOW bit from the RF_FSM_CTRL register is high. Since the IRQ is tied to the near overflow flag of the FIFO, it can be cleared by emptying the FIFO.

The IRQs can be activated by the RF_REG03_IRQ_CONF_IRQS_MASK field of the RF_REG03 register. For example, the IRQ RXSTOP status can be activated by setting bit 1 of the RF_REG03_IRQ_CONF_IRQS_MASK field to 1. By default, the IRQs are active high, but this behavior can be switched by writing 1 to the RF_REG03_IRQ_CONF_IRQ_ACTIVE_LOW field of the RF_REG03_ register.

In addition, the pad can also be configured to be in High-Z state when the IRQ is not active, by setting to 1 the RF_REG03_IRQ_CONF_IRQ_HIGH_Z field of the same register.

For example, to enable the IRQ RXSTOP status, the following code can be used:

RF->REG03 |= IRQ_CONF_IRQS_MASK_RX_STOP;

NVIC_EnableIRQ(RF_RXSTOP_IRQn);

## FIFOs

There are two 128-byte FIFOs: one for the RX and one for the TX.

### Accessing the FIFOs and FIFO Status

The two FIFOs’ data are accessible via the RF_TXFIFO and RF_RXFIFO registers. This access can be achieved in burst mode without having to manually increment addresses. A write to the RF_TXFIFO register corresponds to a push, while a read to the RF_RXFIFO register corresponds to a pop. Reading the RF_TXFIFO register is possible, but there is no action on the FIFO (no pop implied). Writing to the RF_RXFIFO register is not possible and would have no impact, as it is read-only.

The status of each FIFO can be read in the RF_FSM_CTRL_RXFIFO_STATUS_* and RF_FSM_CTRL_TXFIFO_STATUS_* fields of the RF_FSM_CTRL register. There are indications regarding overflows, underflows, and whether the FIFO is empty or full. The RF_FSM_CTRL_*XFIFO_STATUS_*X_NEAR_OVERFLOW and RF_FSM_CTRL_*XFIFO_STATUS_X*_NEAR_UNDERFLOW fields of the RF_FSM_CTRL register are controlled by the value of the RF_REG03_FIFO_FIFO_THR[2:0] field in the RF_REG03 register for the RX and the value of the RF_REG03_FIFO_2_FIFO_THR_TX[2:0] in the same register for the TX. In the "Available FIFO Thresholds" figure, the thresholds for the value of RF_REG03_FIFO_FIFO_THR are given. The FIFOs can be flushed at any time by setting bit 0 of the respective status registers to 1. Alternatively, the FIFOs can be flushed at the beginning of a reception (RX case) or at the end of a transmission (TX case).

Figure: Available FIFO Thresholds

If the bit RF_PACKET_EXTRA_PACKET_EXTRA_FIFO_REWIND of register RF_PACKET_EXTRA is set to 1, then after a TX transmission, the TX FIFO is reset to its previous stage. This function allows the sending of the same packet several times without the necessity of filling the FIFO every time.

During the reception of a message, many events can occur: a CRC error, a packet length error, etc. In all cases, the data has to be stored in the FIFO, at least temporarily. If a given event occurs, there are two choices: keep the data in the FIFO and let the external controller examine the content, or simply flush the received data. To avoid a situation in which the user application starts to look at the FIFO’s content before the end of the packet, it is important that the FIFO status is updated only at the end of the packet. The RX FIFO supports these two features. The automatic flush is controlled by the RF_REG03_FIFO_FIFO_FLUSH_ON_ADDR_ERR, RF_REG03_FIFO_FIFO_FLUSH_ON_PL_ERR, RF_REG03_FIFO_FIFO_FLUSH_ON_CRC_ERR, and RF_REG03_FIFO_FIFO_FLUSH_ON_OVFLW fields of the RF_REG03 register. The RF_REG03_FIFO_RX_FIFO_ACK field of the same register is responsible for choosing the behavior of the FIFO status. If it is set to 1, the packet has to be received correctly before updating the FIFO status.

If software writes to the RF_FSM_CTRL_TX_FIFO_STATUS_TX_FLUSH or RF_FSM_CTRL_RX_FIFO_STATUS_RX_FLUSH fields of the RF_FSM_CTRL register, the FIFO is flushed.

Additionally, if the RF_REG03_FIFO_2_RXFF_FLUSH_ON_START or RF_REG03_FIFO_2_TXFF_FLUSH_ON_START field in the RF_REG03 register is set, the RX FIFO is flushed when the RX is enabled (so a packet with an empty FIFO can be received), or the TX FIFO is flushed after the end of a packet transmission (to provide an empty FIFO).