# Radio Configuration

## Data Rate

The symbol rate is specified indirectly through the RF_REG08_MOD_INFO_*_DR_M_* field of the RF_REG08 register. The RF_REG08_MOD_INFO_*_DR_M_* field specifies the oversampling ratio frequency, but since the oversampling is fixed to 8, it also specifies the symbol rate. It can be calculated using the following equation, where f sys is the system frequency – that is, 16 MHz or 24 MHz:

### Fractional Data Rate

To increase the number of possible data rates, it is possible to have a fractional data-rate, which is a data-rate that is a fraction of the actual data-rate. The effective data rate is given by the following equation, where N and D are the numerator and denominator specified in the RF_REG11_TX_FRAC_CONF_TX_FRAC_NUM and RF_REG11_RX_FRAC_CONF_TX_FRAC_NUM fields in the RF_REG11 register:

The fractional data rate is achieved through interpolation.

In TX, this interpolation adds a gain on the signal, meaning that the modulation index changes. The amplitude is multiplied by the following, where the RF_REG10_FRAC_CONF_TX_FRAC_GAIN bit is specified in the register RF_REG10:

So if D = 10 and RF_REG10_FRAC_CONF_TX_FRAC_GAIN is 0, the gain is equal to 10/8 = 1.25.

For the RX, there is also an amplitude gain due to the fractional data rate. The gain is given by the same calculation as is used in TX. Since the fractional data-rate block is located at the input of the demodulator, this has to be taken into account when calculating the amplitude of the signal at the output of the matched filter (see Matched Filtering).

## Central Frequency

The central frequency can be calculated using the following equation, where f RF is the central RF frequency, and f refTX is the reference frequency – that is, f refTX = 144 MHz:

The RFFE chip has the option of having two different clock references, depending on the operational mode: TX or RX. The TX reference clock is five times larger than the RX clock. To have the same frequency in RX and TX, the digital central frequency needs to be changed. However, the digital block has the capability of switching automatically between the TX value and the RX value. To switch this feature on, the RF_CENTER_FREQ_CENTER_FREQ_ADAPT_CFREQ bit of the RF_CENTER_FREQ register must be set to 1.

NOTE: The meaning of the RF_CENTER_FREQ_CENTER_FREQ_CENTER_FREQUENCY field (in the same register) changes if automatic adaptation is turned on. When it is set to 0, its meaning is that specified in the previous equation.

If it is set to 1, it is specified in the following formula, where f RF is the RF frequency, and f refTX is the reference frequency in TX Mode:

The corresponding frequencies are obtained by dividing the value by 4 for the TX Mode, and by adding this value to the same value divided by 4 in RX Mode.

## Channels

In the RFFE it is possible to work with channels.This means that only a base frequency and the channel spacing need to be specified; then the user needs only to specify the channel wanted. The advantage of this is that channel specification requires only one register access, while the central frequency specification requires four register accesses

This function is activated by setting the RF_CODING_CHANNELS_2_EN_CHANNEL_SEL bit of the RF_CODING register to 1. The channel spacing is specified in the RF_CODING_CHANNELS_1_CHANNEL_SPACING_LO and RF_CODING_CHANNELS_2_CHANNEL_SPACING_HI fields of the RF_CODING register. The value in this field is given by the following formula, where f sp is the channel spacing:

If channel 4 is wanted (that means 4 × fsp from the central frequency), the value 0x4 must be written to the RF_REG08_CHANNEL_CHANNEL field of the RF_REG08 register.

## Pulse Shape

The pulse shape is specified through the RF_TX_PULSE_SHAPE* registers. The pulse shape is composed as follows:

coef_1, coef_2, ... coef_14, coef_15, coef_15, coef_14, ..., coef_2, coef_1

The over-sampling is set to 8; hence, the pulse shape is four symbols long.

If the RF_REG01_MOD_TX_PULSE_NSYM bit of the RF_REG01 register is set to 1, the second half of the pulse shape is inverted.

NOTE: The modulation is obtained by converting both the convolution of the pulse shape and the data-stream into a series of pulses (not rectangles). In the case of a GFSK modulation, the specified pulse shape is not the impulse response of an exponential filter, but the convolution of this response with a rectangle that is 1 symbol long.

## Modulation Index

The modulation index, h, is specified by the following equation, where Δf is the frequency deviation from the central frequency, and DR is the data rate:

After the pulse shaper, the data is multiplied by a specified factor M, and then added to the central frequency. If a series of 1 is assumed, the output of the pulse shape has an output of Q. The modulation index can be rewritten as:

The factor M is specified through mantissa (man) and exponent (exp), by the formula:

Here there are two ways of choosing the modulation index:

- Fix the pulse shape and adapt the multiplication factor to achieve the desired modulation index.
- Fix the multiplication factor and adapt the pulse shape.

The second method is not optimal. In fact, it can occur that the exponent part of the multiplicative factor has to be used. Moreover, there is a loss of granularity if this method is used.

The exponent and the mantissa value can be specified in the RF_REG11 register (RF_REG11_TX_MULT_TX_MULT_EXP and RF_REG11_TX_MULT_TX_MULT_MAN fields).

NOTE: If the interpolator is used, the interpolation gain has to be taken into account.

Example: an MSK modulation at 800 kbps.

A rectangular pulse shape is chosen with a value of 120 (coef_0,.., coef_11 = 0, coef_12...coef_15=120). The value Q is equal to 120: The modulation index for an MSK modulation is 0.5. The multiplicative factor M is:

This value must be split into mantissa and exponent. The exponent is the floor of the log2 of M, which is 2. The resulting mantissa is 13.

In the case of a 4FSK modulation, the definition of index modulation must be considered to be the same, but this results in the additional deviations being at +3 and -3 times the nominal deviation. So, for example, if a 2-FSK configuration is defined for ±250 kHz, it results in the 4FSK version also having ±750 kHz as frequency deviations.

## Interpolator

At the end of the TX chain there is an interpolator. Its main purpose is to avoid quantization steps when the TX is working with low data rates. In fact, a quantization step can result in a wider spectrum. The interpolator is a simple first order cascaded integrator-comb (CIC) interpolator. The input clock is the 8x symbol frequency. The output frequency f out is specified by the RF_REG01_MOD_TX_CK_TX_M(4:0) field of the RF_REG01 register. Its definition is:

The interpolator is enabled using the RF_REG01_MOD_TX_EN_INTERP bit of the same register. If the interpolator is disabled, the output signal is re-sampled at the f out frequency.

NOTE: It is preferable that the f out frequency is an integer multiple of the f in frequency (8x symbol rate).

## Channel Filter Configuration

The channel filter is not a digital block, but is digitally configurable, and its configurations might affect the digital baseband fine tuning. It is a polyphase filter, so its transfer function is not symmetrical; therefore, it rejects the image. Its central frequency and its bandwidth can be configured with three parameters. Both central frequency and bandwidth are tunable via the bias of the transconductance (Gm) of the filter. The bias is also tunable: it is generated by a switched capacitor PTAT, and the frequency of the switched caps can be changed. The frequency is defined by the following equation, where f sys is the RFFE system frequency, and so it is either 16 MHz or 24 MHz, and K f is the value of the field RF_REG_1B_ANACLK_DIV_FILT of the RF_REG_1B register:

The bias of the filter can be tuned via the RF_RSSI_CTRL_FILTER_BIAS_IQ_FI_BW and RF_RSSI_CTRL_FILTER_BIAS_IQ_FI_FC fields of the RF_RSSI_CTRL register.

An approximated configuration of the filter can be made by using the following equations:

For example, in Bluetooth Low Energy technology, RF_REG_1B_ANACLK_DIV_FILTDIV_FILT = 7, RF_RSSI_CTRL_FILTER_BIAS_IQ_FI_FC = 8, and RF_RSSI_CTRL_FILTER_BIAS_IQ_FI_BW = 14, so:

## Phase and RSSI Fractional Decimation

The purpose of the decimation blocks is to change the sampling frequency of the signal from the analog and digital front end to the demodulation blocks; these work with a constant oversampling ratio, while the front end is fully configurable.

In the case of an analog baseband, there are some issues regarding the analog baseband blocks. In fact, the intermodulation frequency needs to be kept high enough to avoid pulling. Moreover, some modulations require a larger bandwidth of the channel filter: this can be achieved only by increasing the clock frequency of the channel filter and the phase ADC.

Resampling is realized with a fractional decimator. (It is supposed that the front end sampling frequency is always higher than the demodulator.) Fractional decimation is realized through an interpolator followed by a decimator. See the "Simplified Block Diagram of the Resampler Block for the Phase" figure.

Figure: Simplified Block Diagram of the Resampler Block for the Phase

Note that in Simplified Block Diagram of the Resampler Block for the Phase (figure), acc stands for “accumulator”, and deriv stands for “derivator”. While the RSSI can be resampled without any major problems, there might be an issue with the phase with this configuration if the signals are not handled correctly. Since it can have a gain that is not a power of 2, the periodicity of the phase cannot be respected. Moreover, because of the implicit filtering, there can be errors when the phase rolls over. This is not the case for the first interpolator, since the first derivation gives the frequency, which has no rollover. The accumulator generates the phase correctly, since in the accumulator the saturation implicitly recreates a good phase. The chosen solution to this issue is to consider the signal to be a frequency, then perform a second order CIC decimator, without the second differentiator. The resulting signal is simply the frequency without a differentiator, and so it is the phase.

There are several parameters that control the phase and RSSI decimation: RF_FRONTEND_FRONTEND_EN_RESAMPLE_PHADC, RF_FRONTEND_FRONTEND_EN_RESAMPLE_RSSI, RF_FRONTEND_FRONTEND_DIV_PHADC, RF_FRONTEND_FRONTEND_RESAMPLE_RSSI_G1, RF_FRONTEND_FRONTEND_RESAMPLE_RSSI_G2, RF_FRONTEND_FRONTEND_RESAMPLE_PH_GAIN, and RF_FRONTEND_RX_IF_DIG_IF_DIG field from the RF_FRONTEND register.

The incoming signals are clocked at the frequency given by the RF_FRONTEND_FRONTEND_DIV_PHADC field of the RF_FRONTEND_FRONTEND register. At the first stage they are upsampled at the f sys frequency, giving a gain of RF_FRONTEND_FRONTEND_DIV_PHADC + 1. At the second stage, the gain is given by the ratio between f sys and the oversampled frequency, and is equal to RF_REG08_MOD_INFO_*_DR_M_* + 1. These gains have to be compensated for, at least to avoid overflows.

Since the phase is converted in frequency and the signal is at an IF, a DC value is present that is amplified during the gain stages. It is interesting to cancel this DC value directly, which can be done using the RF_FRONTEND_RX_IF_DIG_IF_DIG field from the RF_FRONTEND register. The value of this field is given by the following equation, where fIF is the IF frequency, and fR is the frequency at the input of the decimation block:

The phase then has two gain stages, due to the presence of the interpolator and the decimator. The first gain is given by the ratio between the maximum frequency of the RFFE baseband – that is to say, 16 MHz or 24 MHz – and the phADC frequency. This gain is equivalent to:

The second gain stage is due to the presence of the decimator, and is equivalent to the ratio between the maximum RFFE baseband frequency and the oversampled frequency – that is to say, 8x the data rate. This gain is given by:

These gain are compensated for, through the RF_FRONTEND_FRONTEND_RESAMPLE_PH_GAIN: this variable is an unsigned word. The gain is given by:

On the RSSI side, an additional gain is added after the interpolator. This gain is given by 2-RF_FRONTEND_FRONTEND_RESAMPLE_RSSI_G1. A second gain is placed after the decimator, and its value is given by 2-RF_FRONTEND_FRONTEND_RESAMPLE_RSSI_G2.

## Carrier Recovery

### Rough Carrier Recovery

The rough carrier recovery is a simple algorithm that tries to fix the signal frequency average to 0. In the case of an FSK, this corresponds to a threshold determination. The time constant of this algorithm is specified in the RF_REG01_TAU_ROUGH_RECOV_TAU_ROUGH_RECOV field of the RF_REG01 register. Rough carrier recovery is enabled by setting the RF_REG01_CARRIER_RECOVERY_EN_ROUGH_RECOV bit of the RF_REG01 register to 1.

In this block, the IF is also canceled. The IF is specified in the RX_IF_DIG_IF_DIG field of the RX_IF_DIG register. This field is given by the following equation, where f IF is the intermediate frequency and f sym is the symbol rate:

### Fine Carrier Recovery

The fine carrier recovery algorithm uses the decision made on the stream to estimate the carrier error and to fix it. In practice, the decision is converted in amplitude and compared to the actual amplitude. The conversion is made through the RF_REG18_FSK_FCR_AMP1_FSK_FCR_AMP1 bit from the RF_REG18 register, and the RF_REG19_FSK_FCR_AMP2_FSK_FCR_AMP2 and RF_REG19_FSK_FCR_AMP3_FSK_FCR_AMP3 bits from the RF_REG19 register.

In the case of an FSK modulation with 1 bit per symbol, the three values are used to recreate the intersymbol interference (ISI), so three bits of the decision output are used: one corresponding to the present state, one for the previous, and one for the next. So the recreated signal has a value of RF_REG19_FSK_FCR_AMP3_FSK_FCR_AMP3 in the case of a sequence [1;1;1], RF_REG19_FSK_FCR_AMP_FSK_FCR_AMP2 for [1;1;0] or [0;1;1], and RF_REG19_FSK_FCR_AMP1_FSK_FCR_AMP1 for [0;1;0]. Respectively, it is -RF_REG19_FSK_FCR_AMP3_FSK_FCR_AMP3 for [0;0;0], -RF_REG19_FSK_FCR_AMP2_FSK_FCR_AMP2 for [0;0;1] or [1;0;0], and -RF_REG19_FSK_FCR_AMP1_FSK_FCR_AMP1 for [1;0;1].

In the case of a 4FSK, the mapping is done with the decision values of the I and Q signals. When I and Q are equal to [0;0] the recreated signal is -RF_REG18_FSK_FCR_AMP_1_FSK_FCR_AMP1. It is RF_REG18_FSK_FCR_AMP_1_FSK_FCR_AMP1 when I and Q are [0;1], - RF_REG19_FSK_FCR_AMP3_FSK_FCR_AMP3 if I and Q are [1;0], and finally RF_REG19_FSK_FCR_AMP3_FSK_FCR_AMP3 with [1;1]. This configuration can be changed by changing the RF_REG00_FOURFSK_CODING_EN_FOURFSK_CODING field in the RF_REG00 register.

If rough carrier recovery is far from being completed, the +Δf and the – Δf might be on the same side. Hence, the decision block only sees a sequence of 0s or 1s. In such a case, the fine carrier recovery works against the correct center frequency by trying to put the – Δf to match the +Δf, which the fine carrier recovery sees as 1s. For this reason, fine carrier recovery is only applied once the pattern has been detected.

The time constant of the fine carrier recovery block is found in the RF_REG01_TAU_PHASE_RECOV_TAU_PHASE_RECOV field of the RF_REG01 register. The block is enabled by setting the RF_REG01_CARRIER_RECOVERY_EN_FINE_RECOV bit of the RF_REG01 register.

### Carrier Recovery Boundaries

The carrier recovery block can recover the carrier in a specified range. Theoretically the range is expected to be as wide as possible, but there are some limitations. First of all, when there is no signal at the input, the block tries to recover a carrier from the noise. Since the noise is usually white noise, the average is generally null; but this is not always true, especially in the presence of interferers, or noise injected from the digital blocks into the analog path. In these cases, the carrier recovery diverges, and in the presence of a signal it is not able to recover the carrier in time, if the preamble is short. For this reason, a boundary for carrier recovery can be specified through the mantissa RF_REG18_CARRIER_RECOVERY_EXTRA_FREQ_LIMIT_MAN and exponent RF_REG18_CARRIER_RECOVERY_EXTRA_FREQ_LIMIT_EXP fields of the RF_REG18_ register. The boundary of the carrier recovery is given by the following formula, where m is the mantissa, e the exponent, and f sym the symbol frequency:

The mantissa needs to be specified as an unsigned value, while the exponent is signed. The carrier is searched for in the range:

In practice, to calculate these values, this set of equations is used:

Example

In the Bluetooth low energy technology standard, the carrier precision is given by ±150 kHz. This means that fl = 150 kHz. The symbol rate in Bluetooth low energy technology is the same as the bit rate, 1 Mbps. So the first equation is:

Now 0.8 must be expressed with mantissa and exponent.

It is easy to calculate that the closest values are e = -1 and m = 5: these values give K = 0.8125, and a carrier recovery range of ±152 kHz. So freq_lim_man(2:0) = 0b101 and freq_lim_exp(2:0) = 0b111 (the prefix 0b means a binary representation).

### RSSI Detection

The previous algorithms work well on a continuous stream. However, in Packet Mode, when the radio is activated and there is no signal, the noise at the output of the phADC is not white, and carrier recovery is perturbed. To avoid this situation, detection is made on the RSSI to estimate the packet’s arrival. RSSI detection can be made on the absolute value of the RSSI, or on the differential value, or both. Differential detection is activated by setting the RF_REG31_RSSI_DETECT_EN_DIFF_RSSI_DETECT bit of the RSSI_DETECT register, while absolute detection is activated using the RF_REG31_RSSI_DETECT_EN_ABS_RSSI_DETECT bit of the same register. The thresholds are specified in the RF_DEMOD_CTRL_RSSI_DETECT_DIFF_THR_RSSI_DETECT_DIFF_THR and RF_DEMOD_CTRL_RSSI_DETECT_ABS_THR_RSSI_DETECT_ABS_THR fields, respectively, of the RF_DEMOD_CTRL register. If both absolute and differential are activated, the RSSI is detected if the differential value is higher than the threshold, and the absolute value is also higher than its respective threshold. The detection is made on the filtered and corrected RSSI value, so the speed is controlled by the value of the RF_REG19_RSSI_BANK_TAU_RSSI_FILTERING field of the RF_REG19 register. If the RSSI filtering is too low, and too much noise is still present on the RSSI value, an additional filtering can be applied by setting the FR_DEMOD_CTRL_DEMOD_CTRL_RSSI_DET_FILT bit of the register RF_DEMOD_CTRL to 1. This additional filtering is equivalent to a 4-tap FIR with all taps set to 1.

The differential RSSI is not just the simple derivative of the RSSI; because of its structure, it might miss some ramp-up. The differential RSSI is the output of an FIR with the following transfer function, where t is equal to 1, 2, 4, or 6, depending on the value of RF_REG31_RSSI_DETECT_RSSI_DET_DIFF_LL of the RF_REG31 register:

The RSSI detection is fed to a state machine that controls the status of the carrier recovery and other blocks. The detection can be sent directly or can be delayed: the delay is controlled by the RF_REG31_RSSI_DETECT_RSSI_DET_WAIT field of the RF_REG31 register. The delays are:

0b00

no delay

0b01

2 symbol delay

0b10

4 symbol delay

0b11

8 symbol delay

As soon as the state machine receives the RSSI detection, a series of tasks can be launched.

Reset and Slow-down

Once the RSSI ramp is detected, the carrier recovery algorithm is reset, and the Starter Mode is set to 0 – that is to say, carrier recovery slows down. The slow-down lasts for the time necessary to get the sync word read on the delayed path, and is calculated automatically (with some margin).

Carrier Offset Estimation

This is always performed; the only way to block it is to disable RSSI detection. Carrier offset estimation is carried out by accumulating the actual frequency for a variable number of samples. The number of samples is chosen using the RF_REG31_RSSI_DETECT_RSSI_DET_CR_LEN field of the RF_REG31 register. The available values are:

- 0b00: 32 samples -> 4 symbols
- 0b01: 64 samples -> 8 symbols
- 0b10: 128 samples -> 16 symbols
- 0b11: 256 samples -> 32 symbols

This system is supposed to work with an 8-bit preamble, so the first two cases correspond to half of, and the entirety of, the preamble, respectively. The other two cases average on the sync word too; in order to get rid of a biased sync word, sync word bias compensation needs to be switched on.

Sync Word Bias Compensation

After the RSSI ramp is detected, the state machine considers 8 bits of preamble, followed by the sync word. The sync word typically has an average of 0. However, since the sync word can be chosen arbitrarily, there might be a bias on the average. In order to compensate for this bias, the state machine corrects the carrier estimation by reading the content of the RF_SYNC_PATTERN register; this clearly only applies to estimations of 16 symbols or 32 symbols. Sync word bias compensation can be activated by setting the RF_DEMOD_CTRL_SYNC_WORD_CORR_EN_SYNC_WORD_CORR bit of the RF_DEMOD_CTRL register to 1. The amplitude of the compensation is controlled by the RF_DEMOD_CTRL_SYNC_WORD_CORR_SYNC_WORD_BIAS field of the same register, and essentially depends on the modulation index. For a modulation index of 0.5, the value 0x4 needs to be applied.

Early Fine Recovery

Normally, fine recovery is only activated after sync word detection. If the RSSI ramp is detected and carrier recovery is estimated correctly, fine recovery can be turned on earlier. In order to do so, the RF_DEMOD_CTRL_DEMOD_CTRL_EARLY_FINE_RECOV bit of the RF_DEMOD_CTRL register is set to 1.

Enable Pre-Sync Word Detection

The sync word is normally detected only on the delayed path. However, there might be an opportunity to detect the sync word, or at least the end part of it, on the non-delayed path as well. If this is the case, the sync word detection on the delayed path arrives with a deterministic delay, so the state machine can tell precisely how long it has to slow down the system. This functionality is activated by setting the RF_DEMOD_CTRL_DEMOD_CTRL_EN_PRE_SYNC bit of the RF_DEMOD_CTRL register to 1.

Enable Min-Max Detection

An offset is always possible, especially if the transmitter is not sending the central frequency but a 0 or a 1 before the preamble, and if the preamble comes a long time after the PA ramp-up. In such a case, the carrier estimation might be biased. However, an alternative algorithm can be used: it looks at the output of the matched filter for the minimum and maximum values, and sets the threshold at the middle. If this functionality is enabled, the search for the min and max is performed only between the 10th and 42nd symbol after the RSSI detection (in Bluetooth low energy technology, it is from the 3rd and the last bit of the synchronization word). This block must not be activated if the carrier estimation is longer than eight symbols; otherwise it gives a false value, since the early estimation is made on data not yet corrected. The functionality is activated by the RF_DEMOD_CTRL_DEMOD_CTRL_EN_MIN_MAX_MF bit of the RF_DEMOD_CTRL register being set to 1.

Fast Clock Recovery

On the 4FSK modulation, clock recovery is critical because the horizontal eye is quite close. In order to have a clock recovery that performs well, the time constant needs to be increased to filter the excessive noise on the zero crossings. However, during the preamble, the eye is not close at all because there is no inter-symbol interference. The idea is to have a short period during the preamble, in which clock recovery is sped up to get the correct phase quickly. This functionality is activated by setting the RF_DEMOD_CTRL_DEMOD_CTRL_EN_FAST_CLK_RECOV bit of the register RF_DEMOD_CTRL to 1.

### Delay Line Synchronization

For some particular protocols, including Bluetooth low energy technology, there is an additional synchronization mechanism that works well for carrier recovery. This mechanism uses the delay line to look at the synchronization word. When a flaw is found, the mechanism is able to evaluate the frequency offset of the carrier recovery.

NOTE: This mode only works with 32-bit sync words and LSB first. It is enabled by setting the RF_DEMOD_CTRL_DEMOD_CTRL_EN_DELLINE_SYNC_DET bit of the register RF_DEMOD_CTRL to 1.

When this mode is activated, it is recommended that the sync word correction bias be activated by setting the RF_DEMOD_CTRL_SYNC_WORD_CORR_EN_SYNC_WORD_CORR bit in the RF_DEMOD_CTRL register to 1. The RF_DEMOD_CTRL_SYNC_WORD_CORR_SYNC_WORD_BIAS field of the same register also must be set. As a rule of thumb, it needs to be fixed at ~12 × h, where h is the modulation index. The internal correlator looks for a peak. The precision of this peak search can be controlled by RF_REG18_DELAY_LINE_CONF_MAX_ERR_IN_DL_SYNC field in the RF_REG18 register. In practice, it defines the maximum number of errors in the sync word, from 0 to 3.

The correction for carrier recovery is available only after the entire sync word has entered the delay line. This correction needs to be applied to the sync word in order to provide the decision block with a good input. Because of this, the delay line needs to be set to a delay greater than 32 symbols.

There is an additional mode that can be used. The delay line is capable of detecting the sync word, so in theory the sync detection in the deserializer is no longer needed. Moreover, the correlation peak also gives information regarding the optimal sampling position of the sync word: it is in the middle of the peak. This information can be used to trigger clock recovery. So the sync word detection in the delay line can be used to trigger correct packet reception. To enable this functionality, the RF_REG18_DELAY_LINE_CONF_EN_SYNC_OK_DELAY_LINE bit of the RF_REG18 register must be set to 1. In this case, non-causal processing needs to be disabled. This mode gives the minimum delay on packet reception. Note that this mode has been tested only for Bluetooth low energy technology-type modulation.

## Matched Filtering

The matched filter is used in order to filter the signal by maximizing the SNR value. This block is also responsible for choosing the right data representation (phase or frequency). There are actually two FIRs present in the digital baseband: in the case of a PSK modulation they are both used for I and Q signals, while in the case of an FSK modulation the FIR is used for anti-causal processing. This block cannot be disabled.

The filter is an FIR, and the coefficients are specified in the RF_RX_PULSE_SHAPE_RX_PULSE_SHAPE_RX_COEF* fields of the RF_RX_PULSE_SHAPE registers. The FIR is symmetrical and its impulse response is given by:

[coef1, coef2, ... coef7, coef8, coef8, coef7, ..., coef2, coef1

In the case of an FSK modulation, the phase signal at the input of the filter is converted to frequency, and goes through the FIR. In the case of a PSK modulation, the phase is converted to the linear domain by a simple look-up table (LUT), and the I and Q signals go through the filter.

At the output of the filter there is a gain stage. This stage is used to normalize the amplitude of the signal. It is mostly useful in the case of FSK modulation to normalize the modulation index, or in the case of a pre-processing in the RX path that has a non-controllable gain. The gain is specified by a mantissa and exponent combination. The values of these coefficients are specified by the RF_REG11_FILTER_GAIN_GAIN_M and RF_REG11_FILTER_GAIN_GAIN_E fields of the RF_REG11 register. The mantissa has to be specified as an unsigned value and the exponent as a signed value. The gain after the FIR is specified as:

## Clock and Data-Rate Recovery

This block recovers the clock of the signal, and its data rate (inside a specific range): in practice it generates an enabled signal working at the clock frequency.

A distinction has to be made between clock recovery and data-rate recovery:

- Clock recovery refers to the recovery of the sampling instant on the eye diagram. In practice, it is the capacity to determine the best instant in which to sample the signal, in order to avoid ISI and to sample in the middle of the eye.
- Data-rate recovery refers to the capability of determining the transmitter data rate. Generally, data rate recovery is not needed, because the matching of the crystals between the TX and the RX is good enough, and the few tenths of ppm can be recovered by the simpler clock recovery algorithm. However, in some special cases, the mismatch can be too high for simple clock recovery; for example, in the case of a transmitter with only an RC oscillator, accuracy cannot be guaranteed. Note that once the data rate has been recovered, the clock still needs to be recovered. Nothing ensures that once the data rate has been recovered, the sampling instant is in the middle of the eye.

Both clock and data-rate recovery work together on the zero crossings of the signal. In particular, a correlation is made between the input signal and an expected crossing signal.

This block takes several parameters: the time constant fields RF_REF_02_TAU_CLK_RECOV_TAU_CLK_RECOV and RF_REF_02_TAU_DATARATE_RECOV_TAU_DATARATE_RECOV, the data-rate recover limit field RF_REG02_DATARATE_OFFSET_DR_LIMIT, and the data-rate offset field RF_REG02_DATARATE_OFFSET_DATARATE_OFFSET, all from the RF_REG02 register. The time constants determine the time that the block needs in order to achieve clock or data-rate recovery, respectively.

RF_REG02_DATARATE_OFFSET_DATARATE_OFFSET specifies the initial expected data-rate offset. The offset is specified with a signed 8-bit word. The full scale corresponds to 12.5% of mismatch.

RF_REG02_DATARATE_OFFSET_DR_LIMIT specifies the range of data-rate recovery. The values are given in the "Data-Rate Recovery Search Range" table.

Table: Data-Rate Recovery Search Range
dr_limit | Search Range
--- | ---
00 | 0
01 | ±3.125%
10 | ±6.25%
11 | ±12.5%

NOTE: For small data-rate mismatches – for example, if only ppm of crystal oscillators are responsible for a DR mismatch – a simple clock recovery is enough. Also, there is a potential issue in data-rate recovery if carrier recovery is not performed correctly. This issue is seen in the "Data-Rate Recovery Issue" figure.

Figure: Data-Rate Recovery Issue

As the "Data-Rate Recovery Issue" figure shows, data recovery aims to align an internal counter to the zero crossings of the signal. In the case shown by the right-hand image in the "Data-Rate Recovery Issue" figure, the data rate is lowered in order to align the zero crossings. If the carrier is not recovered correctly, the zero crossings are misaligned and appear as though they came from a faster signal. For this reason, the conditions for the zero crossing detection of data-rate recovery are stricter.

Clock recovery does not change in the case of a 4FSK modulation: it is always based on the zero crossing detection. However, because of the 4FSK modulation, the eye diagram horizontal opening is narrower than that of a 2-FSK modulation, as can be seen in "Eye Diagram for 2FSK Modulation and 4FSK Modulation" figure.

Figure: Eye Diagram for 2FSK Modulation and 4FSK Modulation

This means that the time constant for the 4FSK modulation needs to be increased in order to achieve better filtering and be more precise regarding the sampling time. The latter is especially important because, as can be seen in Figure 16, if the sampling time is not exact, there might be a wrong decision regarding the level. The same is not true for the 2-FSK, for which, ideally, the sampling time can be between the two zero crossings.

## Decision

Due to the Gaussian filter, the GFSK modulation scheme introduces inter-symbol interference (ISI). The ISI decreases the sensitivity of the receiver, because during the decision the signal level can be smaller than in the case of a rectangular pulse shape. ISI cancellation is carried out using the Viterbi algorithm.

### Viterbi Algorithm

The most elegant solution for getting rid of ISI is the Viterbi algorithm, because it is a maximum likelihood sequence estimator.

The Viterbi algorithm is simply enabled by setting the RF_REG19_DECISION_EN_VITERBI_GFSK bit of the RF_REG19 register. The amplitudes of the expected signal are specified in the RF_REG18_FSK_FCR_AMP_1_FSK_FCR_AMP1 field in the RF_REG18 register, and the RF_REG19_FSK_FCR_AMP_2_FSK_FCR_AMP2 and RF_REG19_FSK_FCR_AMP_3_FSK_FCR_AMP3 fields in the RF_REG19 register. The path length of the estimator is specified by the RF_REG19_DECISION_VITERBI_LEN field of the RF_REG19 register.

## RSSI Filtering and AGC

The RSSI filter is a block that filters the instantaneous RSSI; the filter is a multi-rate filter, so a large choice of filter rates is available. The time constant of the filter is given by the RF_REG19_RSSI_BANK_TAU_RSSI_FILTERING field in the RF_REG19 register. A fast mode can also be made available, by setting the RF_REG19_RSSI_BANK_FAST_RSSI bit of the same register to 1: this results in the time window being eight times shorter. During the averaging period, two blocks also evaluate a minimum and a maximum value of the RSSI. These RSSI values are available in the RF_REG45_RSSI_AVG_RSSI_AVG bit from the RF_REG45 register and the RF_RSSI_MIN_MAX_RSSI_MAX_RSSI_MAX and RF_RSSI_MIN_MAX_RSSI_MIN_RSSI_MIN bits from the RF_REG45 register. Note that the controlled (AGC) attenuation in the RX signal path is compensated for automatically by the block, so these values have to be considered absolutes.

The RSSI-filtered value is also used by an AGC algorithm. The AGC consists of a simple counter. If the RSSI-filtered value is greater than the value specified in the RF_REG1D_AGC_THR_HIGH_AGC_THR_HIGH field from the RF_REG1D register, the counter increases; if it is lower than the value specified in the RF_REG1D_AGC_THR_LOW_AGC_THR_LOW bit from the same register, the counter decreases. The counter has three bits and starts at 0. Its maximum value is fixed by the value of the RF_REG1D_ATT_CTRL_ATT_CTRL_MAX field of the RF_REG1D register. The value of the counter is then used as the input of the AGC look-up table specified in the RF_AGC_LUT* registers. This LUT is composed of 11-bit words that correspond to the attenuation of the analog RX path. The bits of the fields of the RF_AGC_LUT_* registers are distributed in the following order:

- agc_level(1:0) — LNA2 configuration
  - 00: max gain
  - 01: 6 dB attenuation
  - 10: not valid setting
  - 11: 12 dB attenuation
- agc_level(2): if set, adds 6 dB of attenuation by LNA current reduction (changed mirror ratio).
- agc_level(3): if set, adds 5 dB of attenuation by LNA1 load resistive degeneration.
- agc_level(4): if set, adds 5 dB of attenuation by LNA1 load resistive degeneration.
- agc_level(6:5) — intermediate frequency amplifier Gm control
  - 00: max gain
  - 01: 6 dB attenuation
  - 10: not valid setting
  - 11: 12 dB attenuation
- agc_level(8:7) — load of the intermediate frequency amplifier
  - 00: 16 kΩ, max gain
  - 01: 8 kΩ, 6 dB of attenuation
  - 10: 4 kΩ, 12 dB of attenuation
  - 11: 2 kΩ, 18 dB of attenuation
- agc_level(10:9) — select the LNA bias current.
  - 00: lna_agc_bias_0
  - 01: lna_agc_bias_1
  - 10: lna_agc_bias_2
  - 11: lna_agc_bias_3

To increase the speed of the AGC, an improved version of the AGC algorithm has been implemented. When an RSSI value is received, the AGC predicts the AGC step. To do so, it needs to know the attenuation between every AGC level. These attenuations can be specified by the RF_AGC_ATT*_RF_AGC_ATT_*_RF_AGC_ATT* fields of the RF_AGC_ATT* registers. The field RF_AGC_ATT1_AGC_ATT_1_AGC_ATT_01 from the RF_AGC_ATT1 register, for example, specifies the attenuation level between level 0 and level 1 of the AGC. These steps must be specified with a resolution of 2 dB. For example, the value 0x3 means that the AGC step attenuates by 6 dB. The attenuations can be optionally specified between 4 dB and 11 dB, with a resolution of 1 dB. In such a case, the value 0x3 means that the AGC step attenuates by 4+3 = 7 dB. To activate the mode of RSSI correction, the RF_RSSI_CTRL_RSSI_CTRL_AGC_MODE bit of the register RF_RSSI_CTRL needs to be set to 1.

The stability of the AGC can be improved for both algorithms by setting a wait state after the AGC changes its state. The AGC algorithm can wait 0, 1, 2, or 3 RSSI measurements before updating the AGC state. This wait time can be selected using the RF_RSSI_CTRL_RSSI_CTRL_AGC_WAIT field of the RF_RSSI_CTRL register.

The AGC algorithm can be switched off by setting the RF_RSSI_CTRL_RSSI_CTRL_BYPASS_AGC bit of the RF_RSSI_CTRL register to 1. The RX chain attenuation is then determined by the RF_REG1D_ATT_CTRL_SET_RX_ATT_CTRL field of the RF_REG1D register.

### Peak Detector

The peak detector is used to increase the adjacent channel rejection in case of a close interferer. If the interferer is strong enough to trigger the peak detector, an AGC step increase is requested. This procedure is repeated until the peak detector trigger returns to zero.

To use the peak detector, the FSM needs to activate it: the RF_REG2D_CTRL_RX_USE_PEAK_DETECTOR of the RF_REG2D register needs to be set to 1. The AGC algorithm uses the peak detector information if the RF_REG1D_AGC_PEAK_DET_EN_AGC_PEAK bit of the RF_REG1D register is set to 1. The peak detector has three thresholds; the AGC algorithm uses one of these thresholds to determine if the interferer is too strong, and another one to determine that no more interferer is present. These two thresholds are selected via the RF_REG1D_AGC_PEAK_DET_PEAK_DET_THR_LOW field and the RF_REG1D_AGC_PEAK_DET_PEAK_DET_THR_HIGH bit of the RF_REG1D register. In the same register there is also the RF_REG1D_AGC_PEAK_DET_PEAK_DET_TAU field, which defines a time constant for the filtering of the peak detector signals.

- RF_REG1D_AGC_PEAK_DET_PEAK_DET_THR_LOW — peak detector low threshold (AGC decrement indicator)
  - 00: below level 1
  - 01: below level 2
  - 10: below level 3
  - 11: N.A
- RF_REG1D_AGC_PEAK_DET_PEAK_DET_THR_HIGH — peak detector high threshold (AGC increment indicator)
  - 0: above level 2
  - 1: above level 3

### RSSI and Peak-Detector Combined AGC Strategy

If the peak detector is activated, there are 4 distinct signals:

rssi_over

Set to 1 if the RSSI value is larger than RF_REG1D_AGC_THR_HIGH_AGC_THR_HIGH.

rssi_under

Set to 1 if the RSSI value is smaller than RF_REG1D_AGC_THR_LOW_AGC_THR_LOW.

peak_over

Set to 1 if the peak detector output is larger than RF_REG1D_AGC_PEAK_DET_PEAK_DET_THR_HIGH.

peak_under

Set to 1 if the peak detector output is smaller than RF_REG1D_AGC_PEAK_DET_PEAK_DET_THR_LOW.

These signals define the following actions:

inc_att (increase attenuation)

Set to 1 if rssi_over or peak_over is 1.

In this case, the required number of steps is estimated using the RSSI value above RF_REG1D_AGC_THR_HIGH_AGC_THR_HIGH; the peak detector alone increases by one AGC step per cycle.

dec_att (decrease attenuation)

Set to 1 if rssi_under and peak_under are 1.

Attenuation is always decreased by one AGC step per cycle.