## Clock Configuration Function Documentation

### Sys_Clocks_XTALClk_Wait

void Sys_Clocks_XTALClk_Wait()

Waits for the XTAL clock to start with a timeout using system clock counter.

Location: clock.h:49

### Sys_Clocks_RCSystemClkConfig

void Sys_Clocks_RCSystemClkConfig(uint32_t cfg, uint32_t rc_cfg)

Configure the RC oscillator and system clock.

Location: clock.h:114

Parameters

Direction | Name | Description
--- | --- | ---
in | cfg | Configuration of the system clock source and prescale value; use SYSCLK_CLKSRC_[RCCLK | STANDBYCLK | RFCLK | JTCK], and JTCK_PRESCALE_*
in | rc_cfg | Configuration for the RC oscillator

Example Code for Sys_Clocks_RCSystemClkConfig
// Enable RC oscillators, set 12 MHz multiplier for start RC oscillator // Set nominal trim settings for RC oscillators Sys_Clocks_RCSystemClkConfig(SYSCLK_CLKSRC_RCCLK, RC_OSC_12MHZ | RC_OSC_ENABLE | RC32_OSC_NOM | RC_OSC_NOM);

### Sys_Clocks_SystemClkConfig

void Sys_Clocks_SystemClkConfig(uint32_t cfg)

Configure the system clock.

Location: clock.h:138

Parameters

Direction | Name | Description
--- | --- | ---
in | cfg | Configuration of the system clock source and prescale value; use SYSCLK_CLKSRC_[RCCLK | STANDBYCLK | RFCLK | JTCK], and JTCK_PRESCALE_*

Assumptions

The flash delay configuration is correct for the previously selected system clock source and frequency; if also changing the RC oscillator frequency, use Sys_Clocks_RCSystemClkConfig()

Example Code for Sys_Clocks_SystemClkConfig
// Set SYSCLK source to the RF clock. Sys_Clocks_SystemClkConfig_Example(SYSCLK_CLKSRC_RFCLK)

### Sys_Clocks_XTALClkConfig

void Sys_Clocks_XTALClkConfig(uint32_t xtal_prescaler)

Configure the 48 MHz XTAL Oscillator.

Location: clock.h:151

Parameters

Direction | Name | Description
--- | --- | ---
in | xtal_prescaler | Configuration of the 48MHz XTAL Oscillator as clock and its prescale value; use CK_DIV_1_6_PRESCALE_[NO_CLOCK_BYTE | 1_BYTE | 2_BYTE | 3_BYTE | 4_BYTE | 5_BYTE | 6_BYTE],

Example Code for Sys_Clocks_XTALClkConfig
// Configure the RFCLK to 8 MHz, using the 48 MHz external crystal. Sys_Clocks_XTALClkConfig(CK_DIV_1_6_PRESCALE_6)

### Sys_Clocks_DividerConfig

void Sys_Clocks_DividerConfig(uint32_t uartclk_freq, uint32_t sensorclk_freq, uint32_t userclk_freq)

Configure the clock divisors for a standard configuration:

Location: clock.h:231

Parameters

Direction | Name | Description
--- | --- | ---
in | uartclk_freq | Target frequency for the UART clock
in | sensorclk_freq | Target frequency for the sensor clock
in | userclk_freq | Target frequency for user clock; if the target frequency exceeds the system clock frequency and the RF clock is available, USERCLK will be sourced from RF clock.

- SLOWCLK (1 MHz)
- BBCLK (8 MHz)
- DCCLK (4 MHz)
- CPCLK (166 kHz)
- UARTCLK as per uartclk_freq
- SENSOR_CLK as per sensorclk_freq
- USERCLK as per userclk_freq

If an exact configuration cannot be found for the desired frequency, the clock divisor will be set to ensure the divided clock does not exceed the specified target frequency.

Assumptions

The system clock has previously been configured.

Example Code for Sys_Clocks_DividerConfig
// Set UARTCLK to 115200 Hz // Set SENSORCLK to 1000 Hz // Set USERCLK to 1000000 Hz // Set other clocks to typical values: // SLOWCLK set to 1 MHz // BBCLK set to 8 MHz // DCCLK set to 4 MHz // CPCLK set to 125 kHz Sys_Clocks_DividerConfig(115200, 1000, 1000000)