# Clock Distribution

## System Clock (SYSCLK)

The system clock (SYSCLK) is the primary clock for the RSL15 system and for all other clocks (except STANDBYCLK). The internal clock structures for the RF front-end are derived from SYSCLK.

The CLK_SYS_CFG_SYSCLK_SRC_SEL bit field from the CLK_SYS_CFG register is used to configure the source for this clock. The sources of this clock can be the following:

- The RC oscillator output (RCCLK; default configuration)
- The standby RC oscillator (through STANDBYCLK)
- The 32 kHz crystal oscillator (through STANDBYCLK)
- The divided 48 MHz crystal oscillator output (RFCLK)
- The JTCK (SWCLK) input signal
- EXTCLK, as provided at the GPIO specified by the GPIO_SRC_EXTCLK register

SYSCLK is typically sourced only through STANDBYCLK when operating in Standby Mode where it is inefficient to go to Sleep Mode, but there is a period of time when the system does not need to process RF traffic or other data. If the clock source for SYSCLK is routed through STANDBYCLK, the following divided forms of SYSCLK are sourced directly from SYSCLK:

- SLOWCLK and divided forms of SLOWCLK (SLOWCLK_DIV2, SLOWCLK_DIV32)
- DCCLK
- CPCLK

If the clock source for SYSCLK is the SWCLK/JTCK input, the frequency of the input clock must be controlled to ensure SYSCLK remains valid.

SYSCLK can be output through one or more GPIO pads using the GPIO components. For more information about the GPIO configuration, see Functional Configuration.

IMPORTANT: When the RSL15 system is processing RF traffic that uses the Bluetooth low energy baseband, SYSCLK must be sourced appropriately to provide the necessary BBCLK frequencies. For more information about limitations on BBCLK, see Baseband Timer Registers.

NOTE: For optimal performance of the RSL15 system, user applications need to use the standard calibration configurations of the RC clock sources provided for the device whenever possible, as described in the Manufacturing Records section of the RSL15 Firmware Reference.

## Standby Clock (STANDBYCLK)

The RSL15 system includes a standby clock (STANDBYCLK) that is used as the source for the RTC (see Real Time Clock (RTC)), and can be used as the source for SYSCLK in standby operating modes.

STANDBYCLK is sourced from one of either the RC32K oscillator, or the XTAL32 oscillator.

The selection of the STANDBYCLK is done by XTAL32K ready. When XTAL32K is ready, the XTAL32K is selected. If XTAL32 is not ready, the RC32K is selected. As the switch of these clock sources is not glitch free, enable only one of them. This avoids possible glitches on the standby clock, and saves power by keeping both oscillators from being enabled at the same time. The selection of the STANDBYCLK clock source is also not glitch-free. Enable/disable the STANDBYCLK clock source only when SYSCLK is not set to STANDBYCLK.

If both sources are disabled, the RC32K becomes enabled during startup and while entering standby mode. If the XTAL is enabled but not ready (i.e. it is not ready, the external XTAL is not present, or there is a defect), the enabling of RC32K is set to guarantee that the system will operate.

We recommend that you use the 32 kHz crystal oscillator instead of the standby RC oscillator, due to:

- Improved clock accuracy
- Simplification of system designs
- Lower power consumption

NOTE: STANDBYCLK is typically configured to be sourced from a 32768 kHz clock source. If STANDBYCLK is supplied at a different frequency, a correction factor can be applied to the timers that drive RF traffic to support input clock frequencies in the range from 25 kHz to 100 kHz. For more information, see Bluetooth Low Energy Baseband Controller.

IMPORTANT: In typical configurations, the RSL15 Bluetooth stack is provided with a 32 kHz crystal oscillator source that provides 32768 Hz frequency with a variation of up to 500 ppm. If STANDBYCLK is within these tolerances, add the LowPowerClock_Source_Set(0) API function call from the Bluetooth stack library to the firmware Bluetooth Low Energy stack initialization procedure, to inform the Bluetooth stack that standard STANDBYCLK meets the low-power clock requirements for the stack. If STANDBYCLK does not meet these operating assumptions, the stack must be informed using the LowPowerClock_Source_Set(1) API function call. In such a case, the RSL15 Bluetooth stack must also be provided with the actual frequency of STANDBYCLK by setting the RTC clock period using the RTCCLK_Period_Value_Set() API function from the Bluetooth stack library. Otherwise, issue the LowPowerClock_Source_Set(1) function call, and provide the frequency of STANDBYCLK via the RTCCLK_Period_Value_Set() function. In addition, the following conditions need to be met: If the clock source is stable with a variation of less than 500 ppm, the period can be set once during initialization and used throughout the execution of an application. For all other clock sources that have a higher error rate, or that might vary over time due to changes in environmental conditions, the application needs to periodically measure and update the RTC clock period. For more information on measuring the RTC clock period, see Asynchronous Clock Counter.

STANDBYCLK can be output through one or more GPIO pads using the GPIO components. For more information about the GPIO configuration, see Functional Configuration.

## Slow Clock (SLOWCLK)

Slow clock (SLOWCLK) is a prescaled form of SYSCLK that is used as an intermediate divided clock for system components that need a lower maximum clock frequency. This clock must always be set to 1 MHz, and is used as the clock source for:

- CPCLK (Power Supply Clocks)
- LIN (see LIN)
- LSAD (see LSAD)

SLOWCLK can also be optionally used as the source for PWM (see PWM).

Further divided forms of SLOWCLK (SLOWCLK_DIV2, SLOWCLK_DIV32) are used as the source for:

- The general purpose timers, which select between SLOWCLK_DIV2 and SLOWCLK_DIV32 (see Timers)
- The watchdog timer, which uses SLOWCLK_DIV32 (see Watchdog Timer)

SLOWCLK is derived from SYSCLK through a 6-bit integer division by the CLK_DIV_CFG0_SLOWCLK_PRESCALE bit field in the CLK_DIV_CFG0 register. This prescaler provides a clock prescaled from SYSCLK by 1 to 64, and results in a SLOWCLK with a frequency defined by the following equation:

SLOWCLK can be output through one or more GPIO pads using the GPIO components. For more information about the GPIO configuration, see Functional Configuration.

## Baseband Clock (BBCLK)

The Bluetooth low energy baseband uses three clock sources:

1. Baseband clock (BBCLK)
2. Divided baseband clock (BBCLK_DIV)
3. Baseband timer clock

For more information about these clocks and timing in the Bluetooth low energy baseband, see Baseband Timer Registers.

## Real Time Clock (RTC)

The real-time clock (RTC) allows a device to track the current time or the time elapsed since the application has started tracking time. The RTC is based on the RTC timer, which is a 32-bit free-running count-up timer.

The RTC is controlled using the ACS_RTC_CTRL register in these ways:

- The RTC is enabled by setting the ACS_RTC_CTRL_ENABLE bit.
- The RTC is disabled by setting the ACS_RTC_CTRL_DISABLE bit.
- The current RTC counter value is reset by setting the ACS_RTC_CTRL_RESET bit.

The current state of the RTC can be queried using the ACS_RTC_CTRL_ENABLE_STATUS bit from the ACS_RTC_CTRL register.

IMPORTANT: In the RSL15device, back-to-back writes to ACS block, or mixing writes to the ACS block with a DMA access to a peripheral can corrupt the values stored to the ACS_RTC_COUNT and ACS_RTC_SECONDS registers when the RTC is updated. To avoid these issues, the Sys_ACS_WriteRegister() function from the HAL library must be used for all writes to ACS registers when using the RTC.

The RTC timer is incremented based on STANDBYCLK or a GPIO input (selected from GPIO0 to GPIO3). To select the clock source for the RTC timer (including selecting no clock as the source for the RTC timer), configure the ACS_RTC_CFG_CLK_SRC_SEL bit-field from the ACS_RTC_CFG register. Only change the source for the RTC when the RTC is disabled. For information about configuring the clock source used by the RTC and RTC timer, see Standby Clock (STANDBYCLK).

The RTC timer updates the RTC once per second. The current RTC value can be read uing the ACS_RTC_SECONDS register.

IMPORTANT: The current RTC timer value can be read through the ACS_RTC_COUNT register, but reads of this register from the ACS are transferred byte-wise from the analog components to the digital systems. As such, reads of the ACS_RTC_COUNT register are non-atomic and the Sys_RTC_Value() function from the hardware abstraction layer (HAL) needs to be used when reading this register. For more information about the HAL library, refer to the RSL15 Firmware Reference.

When a wakeup event occurs during sleep mode, the eight least significant bits of the current RTC timer counter value are copied into the ACS_WAKEUP_STATE_RTC_VALUE bit-field in the ACS_WAKEUP_STATE register. This field can be used to precisely identify when a wakeup event has occurred relative to the current time.

NOTE: To simplify testing, RTC timer pulses can be manually applied by writing the ACS_RTC_CTRL_FORCE_CLOCK bit in the ACS_RTC_CTRL register. Each time this bit is written, an RTC timer clock pulse is generated. The current RTC timer count can also be manually set by loading the desired value to the ACS_RTC_COUNT_LOAD register. Only use this test bit and register when no clock source is selected for the RTC.

The RTC supports three events, as configured using the ACS_RTC_CTRL register. These events are:

RTC Clock

The RTC clock event is enabled when the ACS_RTC_CTRL_ENABLE_CLOCK_EVENT bit is set, and disabled when the ACS_RTC_CTRL_DISABLE_CLOCK_EVENT bit is set. The current configuration of the RTC clock event can be queried using the ACS_RTC_CTRL_ENABLE_CLOCK_EVENT_STATUS bit.

If enabled, the RTC clock event generates a wakeup signal and an interrupt when the RTC timer update triggers a rising edge on a bit between 10 to 17 of the RTC timer counter, supporting a configuration of the RTC clock event for an update interval of between 62.5 ms and 8 s. The bit selected for this update is configured using the ACS_RTC_CFG_RTC_CLOCK_SRC bit-field from the ACS_RTC_CFG register.

NOTE: The ACS_RTC_CFG_RTC_CLOCK_SRC bit must not be updated while the RTC clock event is enabled.

The wakeup event flag for the RTC clock event must be cleared between events to allow the generation of a new wakeup signal and interrupt.

RTC Alarm

The RTC alarm event is enabled when the ACS_RTC_CTRL_ENABLE_ALARM_EVENT bit is set, and disabled when the ACS_RTC_CTRL_DISABLE_ALARM_EVENT bit is set. The current configuration of the RTC alarm event can be queried using the ACS_RTC_CTRL_ENABLE_ALARM_EVENT_STATUS bit.

If enabled, the RTC alarm event generates a wakeup signal and an interrupt when the RTC timer exceeds the threshold defined by the value stored to the ACS_RTC_COUNT_THRES register.

NOTE: The ACS_RTC_COUNT_THRES register must not be updated while the RTC alarm event is enabled.

The wakeup event flag for the RTC alarm event must be cleared between events to allow the generation of a new wakeup signal and interrupt.

RTC Overflow

The RTC overflow event is enabled using the ACS_WAKEUP_CFG_RTC_OVERFLOW_EN bit in the ACS_WAKEUP_CFG register. If enabled, the RTC overflow event generates a wakeup signal when the RTC timer counter wraps to 0. The wakeup event flag for the RTC overflow event must be cleared between events to allow the generation of a new wakeup signal.

### RTC Output Control

The ASC_AOUT_CTRL register can be used to periodically output the RTC on GPIO 0 to control the timing of an external device. Configuration options include:

RTC Start

The ACS_AOUT_CTRL_RTC_CLOCK_GPIO0_START bit-field is used to configure how often the RTC output starts. This is configurable in power of 2 multiples of 125 ms (assuming a 32.768 kHz clock frequency).

RTC Stop Source and Edge

The ACS_AOUT_CTRL_RTC_CLOCK_GPIO0_STOP_SRC bit-field and ACS_AOUT_CTRL_RTC_CLOCK_GPIO0_STOP_EDGE bit are used to configure when the RTC output signal stops. The stop signal can be triggered on an event on GPIO 0 to 3, and on either a rising or a falling edge.

NOTE: Selecting GPIO 0 as the stop source triggers a single pulse. Use of the rising edge as the stop event trigger results in a 1 cycle high pulse, and use of the falling edge of the stop event results in a half period high pulse.

IMPORTANT: The ACS_AOUT_CTRL register is also used to configure the analog test output (AOUT) signal. Care must be taken when using this register for both use cases, to avoid zeroing out the AOUT configuration when configuring for RTC output (and vice versa).

## User Clock (USRCLK)

The user clock is an output clock that you can use as a clock source for the PCM interfaces or for any external components. This clock is not used internally by the RSL15 system, so its usage can depend entirely on the outside needs of the larger system containing RSL15.

USRCLK is derived from SYSCLK or RF BBCLK through a 12-bit integer division by the CLK_DIV_CFG2_USRCLK_PRESCALE bit field in the CLK_DIV_CFG2 register. The source for USERCLK can be selected using the CLK_DIV_CFG2_USRCLK_SOURCE_SEL bit from the CLK_DIV_CFG2 register. This prescaler provides a clock prescaled from SYSCLK or RF BBCLK by 1 to 4096, and results in a USRCLK with a frequency defined by the following equation:

USRCLK can be output through one or more GPIO pads using the GPIO components. For more information about the GPIO configuration, see Functional Configuration.

## Power Supply Clocks

The following power supply components each have their own clock sources:

- The VDDCP charge pump is clocked using CPCLK, which is divided from SLOWCLK. Configuration and restrictions on this clock are described in Charge Pump Supply Voltage (VDDCP).
- The DC-DC buck converter is clocked using the DCCLK, which is divided from SYSCLK. Configuration and recommendations for this clock are described in DC-DC Converter (VCC).

## Interface Clocks

The following interface components each have a clock divided from SYSCLK that is used to clock the interface:

I2C

The I2C clock is only used by the I2C interface when the interface is configured for controller mode. For information about configuring the I2C clock, see I2C Interfaces.

PWM

For more information about this interface and its clocks, see PWM.

SPI

For more information about these interfaces and their clocks, see Serial Peripheral Interfaces (SPI).

UART

The UART interface indirectly divides SYSCLK to achieve the baud rate for UART communications. For the UART TX output, this baud rate is applied directly; for the UART RX input, this baud rate is used in the asynchronous recovery of data from this pad. For more information about this interface and its clock, see Universal Asynchronous Receiver-Transmitter (UART) Interfaces.

The following interface components each have a clock divided from SLOWCLK that is used to clock the interface:

LIN

For more information about this interface and its clocks, see LIN.

LSAD

The LSAD channels use either SLOWCLK or SLOWCLK divided by a fixed divisor of 5 to sample analog signals. Information on the LSAD interface clocking and sample configuration can be found in LSAD.

The following interface components are special cases, which have more flexible clock assignments:

PCM

The PCM interface does not have its own divided clock, but is asynchronously clocked relative to the clock input provided at the PCM clock input pad. This clock source can be provided in the RSL15 system by routing a clock output to the same GPIO that is acting as the PCM clock input (see Functional Configuration for more information about configuring a GPIO as both a clock output and a PCM clock input; see Pulse Code Modulation (PCM) Interface for more information about the PCM interface).

Sensor Interfaces

The SAR-ADC, pulse counter, and ultra-low-power (ULP) data acquisition subsystem are all clocked using the SENSOR_CLK signal. This clock is enabled using the CLK_CFG1_SENSOR_CLK_DISABLE bit from the CLK_DIV_CFG1 register. The source for this clock signal is selected using the SENSOR_CFG_CLK_SEL bit from the SENSOR_CFG register.

If standby clock (STANDBYCLK) is selected as the source for this clock, these interfaces always use STANDBYCLK.

If SYSCLK is selected as the source for this clock, SENSOR_CLK is derived from SYSCLK in run mode and uses STANDBYCLK directly when the system is in a hardware-based low power mode. SENSOR_CLK is derived from SYSCLK through an 11-bit integer division by the CLK_DIV_CFG1_SENSOR_CLK_PRESCALE bit field in the CLK_DIV_CFG1 register. This prescaler provides a clock prescaled from SYSCLK by 1 to 2048, and results in a SENSOR_CLK with a frequency defined by the following equation:

For more information about these interfaces and their clocks, see Sensor Interfaces.