### FLASH_DELAY_CTRL

Bit Field | Read/Write | Field Name | Description
--- | --- | --- | ---
7 | RW | READ_MARGIN | Flash Read access time margin
3:0 | RW | SYSCLK_FREQ | Configure Flash, memory and RF power-up delays

Bit Field | Field Name | Value Symbol | Value Description | Hex Value
--- | --- | --- | --- | ---
7 | READ_MARGIN | DEFAULT_READ_MARGIN | Use default read margins | 0x0*
|  | FAST_READ_MARGIN | Use fast read margins | 0x1
3:0 | SYSCLK_FREQ | FLASH_DELAY_FOR_SYSCLK_3MHZ | FLASH_DELAY_CTRLx set for a SYSCLK = 3 MHz | 0x0
|  | FLASH_DELAY_FOR_SYSCLK_4MHZ | FLASH_DELAY_CTRLx set for a SYSCLK = 4 MHz | 0x1
|  | FLASH_DELAY_FOR_SYSCLK_5MHZ | FLASH_DELAY_CTRLx set for a SYSCLK = 5 MHz | 0x2*
|  | FLASH_DELAY_FOR_SYSCLK_8MHZ | FLASH_DELAY_CTRLx set for a SYSCLK = 8 MHz | 0x3
|  | FLASH_DELAY_FOR_SYSCLK_10MHZ | FLASH_DELAY_CTRLx set for a SYSCLK = 10 MHz | 0x4
|  | FLASH_DELAY_FOR_SYSCLK_12MHZ | FLASH_DELAY_CTRLx set for a SYSCLK = 12 MHz | 0x5
|  | FLASH_DELAY_FOR_SYSCLK_16MHZ | FLASH_DELAY_CTRLx set for a SYSCLK = 16 MHz | 0x6
|  | FLASH_DELAY_FOR_SYSCLK_20MHZ | FLASH_DELAY_CTRLx set for a SYSCLK = 20 MHz | 0x7
|  | FLASH_DELAY_FOR_SYSCLK_24MHZ | FLASH_DELAY_CTRLx set for a SYSCLK = 24 MHz | 0x8
|  | FLASH_DELAY_FOR_SYSCLK_48MHZ | FLASH_DELAY_CTRLx set for a SYSCLK = 48 MHz | 0x9