# Architecture

The RSL15 system uses a memory architecture based on the pre-defined memory map of the Arm Cortex-M33 processor.

The implementation of the memory architecture uses a number of single-port memories and memory-mapped registers interconnected with memory buses and support elements. All memories are accessible through the Arm Cortex-M33 possessor, although some interfaces and peripherals such as the DMA and Bluetooth baseband provide additional access paths to specific memory elements. The connections to the components that make up the memory for the RSL15 system are shown in the "System Memory Architecture" figure.

Figure: System Memory Architecture

## Memory Instances

The memory architecture for RSL15, including the memory instances, registers, and other components, are accessible from the Arm Cortex-M33 processor through one or more of the processor’s standard buses. All the memory instances are shown in the "RSL15 Memory Instances" table.

NOTE: RSL15 is produced in two variants with different amounts of flash memory for each variant; the "RSL15 Memory Instances" table below lists memory sizes for each variant, marked as RSL15-512 and RSL15-284 respectively.

Table: RSL15 Memory Instances
Instance Name | Size | Type | Start Address
--- | --- | --- | ---
Boot ROM (Program ROM) | 20 KB | ROM | 0x000000000
Flash Code Redundancy | 2 KB x 2 | Flash | 0x00060000, 0x00060800
Flash Data Redundancy | 256 B x 2 | Flash | 0x00061000, 0x00061100
Flash Non-Volatile Records | 256 B x 8 | Flash | 0x00080000, 0x00080100, 0x00080200, ..., 0x00080700
Flash Code | 352 KB (RSL15-512) | Flash | 0x00100000
264 KB (RSL15-284)
Flash MNVR | 128 B + 128 B | Flash | 00080800
Flash Data | 160 KB (RSL15-512) | Flash | 0x00158000
20 KB (RSL15-284)
Data RAM | 8 KB x 8 | RAM | 0x20000000, 0x20002000, 0x20004000, ..., 0x2000E000
Baseband Data RAM | 8 KB x 2 | RAM | 0x20010000, 0x20012000

The memory instances can be disabled when not in use, to reduce power consumption. The data RAM and baseband data RAM instances can also be placed into a retention mode, where the contents of the memories are maintained but cannot be accessed. In total, there are five memory power states:

Disabled

If the memory instance's corresponding bit in the SYSCTRL_MEM_POWER_STARTUP register is cleared, the memory is in disabled mode. In this mode, memory is not powered and memory isolation is enabled. Memory instances do not retain their state in disabled mode, and are inaccessible.

When a memory instance is in disabled mode, its corresponding bits in the SYSCTRL_MEM_ACCESS_CFG and SYSCTRL_MEM_POWER_ENABLE registers are cleared. To enable a memory instance in disabled mode, the instance must first be placed into the power up or wakeup modes.

Retention

If the data RAM or baseband data RAM memory instance's corresponding bits in the SYSCTRL_MEM_POWER_STARTUP and SYSCTRL_MEM_RETENTION_CFG registers are set, the memory is placed into retention mode when using low power modes. In this mode, the memories are held in a low-power state, and memory isolation is enabled. Memory instances retain their state in retention mode, but are inaccessible.

When a memory instance is in retention mode, the corresponding bits in the SYSCTRL_MEM_POWER_ENABLE and SYSCTRL_MEM_ACCESS_CFG registers are cleared. To enable a memory instance in retention mode, the instance must first be placed into the power up or wakeup modes.

Power up

If the memory instance's corresponding bit in the SYSCTRL_MEM_POWER_STARTUP register is set, and the corresponding bits in the SYSCTRL_MEM_POWER_ENABLE, SYSCTRL_MEM_ACCESS_CFG and SYSCTRL_MEM_RETENTION_CFG registers is cleared, the memory is in power up mode. In this mode, memories are powered one-by-one at 200 ns intervals and held in a normal power state with memory isolation once powered.

This mode is a transitional state between disabled or retention and enabled modes, where memory instances remain inaccessible. Once all memories are powered they are automatically held in the power up state for a minimum of 1.3 μs.

Wakeup

If the memory instance's corresponding bits in the SYSCTRL_MEM_POWER_STARTUP and SYSCTRL_MEM_POWER_ENABLE registers is set, and the corresponding bits in the SYSCTRL_MEM_ACCESS_CFG and SYSCTRL_MEM_RETENTION_CFG registers is cleared, the memory is in wakeup mode. In this mode, memory is powered and held in a normal power state with memory isolation.

This mode is a transitional state between disabled or retention and enabled modes, where memory instances remain inaccessible. Memories are held in the wakeup state for a minimum of 1.3 μs.

Enabled

If the memory instance's corresponding bits in SYSCTRL_MEM_POWER_STARTUP, SYSCTRL_MEM_POWER_ENABLE, and SYSCTRL_MEM_ACCESS_CFG registers are set, the memory is in Enabled mode. In this mode, memory is held in a normal power mode, with memory isolation disabled. Memories are fully functional in enabled mode.

Accesses outside of defined memory areas produce a memory fault or ACCESS_ERROR interrupt. Accesses to a memory that is not in enabled mode produce a bus fault or ACCESS_ERROR interrupt:

| • | If the failed memory access occurs on the Arm Cortex-M33 processor, a memory fault is generated for access outside of a defined memory area and a bus fault is generated for accesses to memories that are not enabled.

| • | If the failed memory access occurs on any other access, an ACCESS_ERROR has occurred. The SYSCTRL_ACCESS_ERROR register indicates if the error occurred on an access from:

| ◦ | The DMA (SYSCTRL_ACCESS_ERROR_DMA_MEM_ERROR)

| ◦ | The Bluetooth baseband (SYSCTRL_ACCESS_ERROR_BB_MEM_ERROR)

| ◦ | The flash copier (SYSCTRL_ACCESS_ERROR_FLASH_COPIER_MEM_ERROR)

| ◦ | The Arm CryptoCell-312 (SYSCTRL_ACCESS_ERROR_CC312_MEM_ERROR)

An ACCESS_ERROR interrupt can also be triggered when the DMA accesses a RAM or peripheral, while the TrustZone security state is not aligned with the DMA security state. If this occurs, the SYSCTRL_ACCESS_ERROR_DMA_PERIPH_ERROR bit in the SYSCTRL_ACCESS_ERROR register is set.

To clear the ACCESS_ERROR interrupt status bits, write SYSCTRL_ACCESS_ERROR_CLEAR to the SYSCTRL_ACCESS_ERROR_ACCESS_ERROR_CLEAR bit from the SYSCTRL_ACCESS_ERROR register.

IMPORTANT: To minimize power consumption, place all unused memories in the disabled state.

## Memory Buses

Buses connected to the Arm Cortex-M33 processor implement the standard Arm Cortex-M33 core memory map. All buses share the same 32-bit Arm Cortex-M33 processor memory space. These buses can also be seen in System Memory Architecture (figure), and are as follows:

Code Bus

Allows the Arm Cortex-M33 processor to fetch instruction and data information from the Arm Cortex-M33 flash memory instances. Instructions can also be fetched from the ROM instance.

System Bus

Allows the Arm Cortex-M33 processor to fetch instructions and data information from the Arm Cortex-M33 core's data memory instances. This bus also provides access to the Bluetooth baseband's data RAM and Peripheral Bus.

Peripheral Bus

Allows the Arm Cortex-M33 processor to access memory-mapped peripherals

DMA Memory Bus

Memory bus shared by the DMA, Arm CryptoCell-312, and flash copier peripherals

## Memory Arbitration

In front of each memory instance, an arbiter manages the simultaneous accesses between the masters - the Arm Cortex-M33 processor (uC), the baseband controller (BB), and the DMA memory bus (DMA).

- Data RAM and peripheral bus accesses use a fixed arbitration scheme where accesses by the Arm Cortex-M33 processor have higher priority than accesses from the DMA (uC > DMA).
- Baseband Data RAM selects between two fixed arbitration schemes:
  - If the baseband is using a divided clock source, the priority order from highest to lowest is the Bluetooth baseband, Arm Cortex-M33 processor, and DMA (BB > uC > DMA).
  - Otherwise, the priority order from highest to lowest is Arm Cortex-M33 processor, DMA, and Bluetooth baseband (uC > DMA > BB).

The DMA Memory Bus also uses a fixed arbitration scheme for accesses, with the priority order of peripheral accesses to the bus being (from highest to lowest priority) the DMA controller, the Arm CryptoCell-312, and the flash copier.