# Timers

The RSL15 system provides five timers, including:

| • | The SysTick timer from the Arm Cortex-M33 core, which is described in SysTick

| • | Four general-purpose timers

Each general-purpose timer provides:

| • | A 24-bit counter

| • | A 3-bit prescale factor that increases by a factor of 2 at each step, scaling between prescalars of 1 through 128.

| • | Three operating modes: single-shot, multiple-shot, and free-run

| • | A dedicated interrupt that can be used to signal timer expiration

| • | Dedicated configuration and status registers

NOTE: Throughout this section, the asterisk * indicates that any of the 4 timer channels, numbered 0-3, can be substituted.

The general-purpose timers are clocked from SLOWCLK, divided by either 2 or 32. The SLOWCLK divisor can be selected using the CLK_SRC bit in the appropriate TIMER*_CFG1 register. The available power of 2 prescaling divisions results in the timers achieving a wider range of timing; however, the granularity at which the timer can be configured to trigger increases in parallel. Use the TIMER_CFG0_PRESCALE bit field to set the power-of-two scaling factor.

After prescaling the timer clock, each timer can be configured to trigger after 1 to 224 cycles of the prescaled clock, by setting the TIMER_CFG0_TIMEOUT_VALUE bit field in the appropriate TIMER*_CFG0 register. The resulting timer delay is equal to:

Where

is equal to SLOWCLK divided by 2 if the CLK_SRC bit in TIMER*_CFG1 is 1, or else it is equal to SLOWCLK divided by 32.

## Starting or Stopping Timers

The state of a timer can be read from the TIMER_CTRL_BUSY bit of its TIMER_CTRL register.

If the timer is not running, it can be started by setting the TIMER_CTRL_START bit of its TIMER_CTRL register. If the timer is running, setting this same bit restarts the timer by reloading the TIMER_CFG0_TIMEOUT_VALUE field in the TIMER_CFG0 register with the initial value.

Each timer can be stopped at any time, by setting the TIMER_CTRL_STOP bit of its TIMER_CTRL register.

In a case where the START and STOP bits are set at the same time, the STOP bit takes precedence over the START bit and the timer is not started.

## Mode Selection

The timers support selection between free-run and single-/multi-shot mode, using the TIMER_CFG1_MODE bit of the TIMER_CFG1 register.

| • | In Free-Run Mode, the timer loads the initial time-out value and counts down to 0. When the value reaches 0, the timer issues an interrupt, reloads the time-out value, and restarts the countdown timer. This process is repeated indefinitely until the timer is explicitly stopped by writing a 1 to the TIMER_CTRL_STOP bit in the TIMER_CTRL register.

| • | In Multi-Shot Mode, the timer loads the initial time-out value and counts down to 0. When the value reaches 0, the timer issues an interrupt, and checks the TIMER_CFG1_MULTI_COUNT bit field in the TIMER_CFG1 register to determine if the countdown timer must be restarted. This process repeats (TIMER_CFG1_MULTI_COUNT + 1) times before the timer is disabled, unless explicitly stopped by the TIMER_CTRL_STOP bit in the TIMER_CTRL register. Single-shot mode is a special case of Multi-shot mode, where the timer is configured to trigger an interrupt only one time.

## GPIO Interrupt Capture Mode

The timers can be used to indicate when a GPIO interrupt occurs. If the timer is configured to monitor GPIO interrupts, and a GPIO interrupt is triggered, the timer stores the current timer value to the TIMER_VAL_CAPTURE register to indicate when the interrupt has occurred.

NOTE: Security levels must be aligned for the GPIO interrupt to be useable by the timer.

To enable GPIO interrupt capture mode, set the TIMER_CFG1_GPIO_INT_ENABLE bit in the TIMER_CFG1 register. To select the GPIO interrupt source used as the trigger for the timer, use the TIMER_CFG1_GPIO_INT_SRC bit-field in the TIMER_CFG1 register.

NOTE: All four GPIO interrupts can be selected as sources for the timer triggers. (See GPIO Interrupts for more information about GPIO interrupts.)

GPIO interrupt mode can be configured to operate in single or continuous mode, using the TIMER_CFG1_GPIO_INT_MODE bit in the TIMER_CFG1 register.

| • | When operating in single mode, the timer captures the timing of one GPIO interrupt. The GPIO interrupt capture mechanism is automatically disabled once the GPIO interrupt is generated. Setting the TIMER_CFG1_GPIO_INT_ENABLE bit high again schedules another single shot capture.

| • | When operating in continuous mode, the timer constantly runs and updates the TIMER_VAL_CAPTURE register when a GPIO interrupt is triggered. The TIMER_CFG1_GPIO_INT_ENABLE bit holds its value in this mode and must be cleared to disable this mode.

When the GPIO-interrupt-based capture is enabled, but the timer is off, the state of the TIMER_VAL_CAPTURE register is preserved.

For more information on configuring GPIO interrupts, see Direct Control.

For registers, see Timers Registers.