# Cyclic Redundancy Check (CRC) Generator

The RSL15 system includes a CRC generator that provides support for two standard cyclic redundancy check (CRC) algorithms (CRC-CCITT and CRC-32, defined by the IEEE 802.3 Ethernet standard). The calculated outputs from this generator can be employed by a user application to ensure data integrity of communications and non-volatile memory information. They do this by guaranteeing that all single-bit errors, two-bit errors, burst errors (i.e., multiple bit errors in a row), and any error containing an odd number of bits can be detected.

NOTE: The integrity of Bluetooth communications is already protected by a 24-bit CRC. The integrity of flash memory words is protected by the flash’s integrated error correction code.

The CRC generator can be configured to select the CRC-CCITT algorithm, by clearing the CRC_CFG_CRC_TYPE bit from the CRC_CFG register to the CRC_CCITT bit setting. The parameters associated with the CRC-CCITT algorithm implementation are provided in the "CRC_CCITT Algorithm Parameters" table.

Table: CRC_CCITT Algorithm Parameters
CRC Parameter | Parameter Value
--- | ---
Order | 16
Polynomial | x16 + x12 + x5 + 1
Polynomial (hex) | 0x1021
Initial Value (hex) | 0xFFFF
Final XOR Value (hex) | 0x0000

No data manipulation is required for the output CRC generated for the standard CRC-CCITT algorithm (i.e., no data byte reversal, reversal of the final result, or other finalization).

The CRC generator can be configured to select the CRC-32 algorithm, by setting the CRC_CFG_CRC_TYPE bit from the CRC_CFG register to the CRC_32 bit setting. The parameters associated with the CRC-32 algorithm implementation are provided in the "CRC_CCITT Algorithm Parameters" table.

Table: CRC_32 Algorithm Parameters
CRC Parameter | Parameter Value
--- | ---
Order | 32
Polynomial | x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1
Polynomial (hex) | 0x4C11DB7
Initial Value (hex) | 0xFFFFFFFF
Final XOR Value (hex) | 0xFFFFFFFF

The output CRC generated for the standard CRC-32 algorithm requires data byte reversal and reversal of the final result.

The CRC generator supports non-standard variants of the CRC-CCITT and CRC-32 standard implementation.

- To use non-standard CRC ordering of data within each data byte, set the CRC_CFG_BIT_ORDER bit from the CRC_CFG register.
- To use non-standard CRC ordering of the final result, set the CRC_CFG_FINAL_CRC_REVERSE bit from the CRC_CFG register.
- To use non-standard CRC XOR of the final result, set the CRC_CFG_FINAL_CRC_XOR bit from the CRC_CFG register. If configured for a non-standard XOR, this uses a final XOR value of 0xFFFF for CRC-CCITT and 0x00000000 for CRC-32.

To use the CRC generator:

1. Write an initial value of 0xFFFF or 0xFFFFFFFF to the CRC_VALUE register.
2. Write to the CRC input registers any data that must be included in the final CRC read from the generator; 1-bit, 8-bit, 16-bit, 24-bit and 32-bit data values are supported. Input data to the CRC generator can be interpreted as either little-endian or big-endian data by selecting the appropriate endian byte ordering, using the CRC_CFG_BYTE_ORDER bit from the CRC_CFG register.
3. At any time, you can read the CRC_FINAL register to obtain the CRC for the data that has been added using the CRC input registers since the last time the CRC_VALUE register was initialized.

For registers, see CRC Registers.