# Power Supply Overview

The power supply tree is powered by the system supply voltage (VCC), which is sourced from one of three supplies:

- Directly from the battery supply voltage (VBAT)
- Indirectly from the battery supply voltage, through the DC-DC buck converter or the internal LDO regulator
- Voltage supplied for the digital I/O pads, including the GPIO and debug port (SWJ-DP) pads (VDDO)

The system supply voltage is used as the source for a number of internal supply voltages, including:

- A regulated, low-noise voltage bandgap reference supply for the analog components (VREF)
- Two configurable regulated supplies for digital components (VDDC, VDDM)
- Two configurable regulated Retention Mode supplies for retaining the digital component state in Sleep Power Mode (VDDCRET, VDDMRET)
- A regulator used in Sleep Power Mode without Retention Mode supplies enabled (VDDACS)
- A configurable regulated supply for the RF front-end (VDDRF)
- An on-chip charge pump for the RF front-end power amplifier, for cases where the TX power requirements exceed the voltage that can be supplied using VDDRF (VDDPA)
- An on-chip charge pump for the other analog system components (VDDA)
- A configurable regulated supply for the flash memory (VDDFLASH)

The "Power Supply Diagram" figure illustrates the RSL15 power supply and related components at a high level.

The digital pins on the device, including the GPIOs, the SWIO & SWCLK pins, and the NRESET pin are also powered by another power supply, VDDO. VDDO is supplied externally to the dedicated VDDO pad.

Figure: Power Supply Diagram

NOTE: VDDC, VDDM, and VDDPA are not available on all packages.

## Power Supply Inputs

### Battery Supply Voltage (VBAT)

The primary voltage supplied to an RSL15 chip is known as the battery supply voltage, because this voltage is supplied by a battery in a typical application.

VBAT directly supplies each of the regulators and charge pumps included in the RSL15 device. This supply voltage is monitored by the power management unit and the voltage monitor to ensure safe system operation, and to signal the current voltage level to user applications. See Power Management Unit for more information.

The minimum VBAT voltage required for basic operation is 1.2 V. The maximum VBAT voltage allowed before damage to the device can result is 3.6 V.

### Digital Output Supply Voltage (VDDO)

The digital output supply voltages are attached to the I/O pads on the RSL15 device. These pads include:

| • | All GPIO pads, as described in General Purpose Input/Output

| • | The NRESET input pad, described in Resets

| • | The SWCLK and SWIO ports, as described in General Purpose Input/Output and Debug Port

The internal system digital logic is attached to the pads through internal level translators. They shift the voltage level from VDDC to the correct VDDO voltage for digital outputs, and translate input digital signals from the correct VDDO voltage to VDDC for digital inputs.

The VDDO input is generally connected externally to VBAT or VDDA, based on the required voltages for digital communications using the associated I/O pads.

IMPORTANT: To minimize power consumption, the VDDO power domain needs to be powered at the lowest voltage possible.

The minimum VDDO voltage required for basic operation is 1.2 V. The maximum VDDO voltage allowed before damage to the device can result is 3.6 V.

## Internal Power Supply Voltages

### DC-DC Converter (VCC)

The System Supply Voltage (VCC) is used as the source for all of the internally generated supply voltages in the RSL15 SoC, and is supplied from VBAT. This power supply is used to reduce the battery voltage from a high voltage range (from 1.2 to 3.6 V) down to a supply voltage in the range from 1.0 to 1.31 V.

The voltage supplied by VCC is configured using the ACS_VCC_CTRL_VTRIM bit-field from the ACS_VCC_CTRL register. This trim setting defines a VCC target, with VCC being supplied directly from the battery, or from either the internal LDO or DC-DC converters. Conditions for each of the different VCC supply configurations can be found in the "VCC Supply Configuration" table.

Table: VCC Supply Configuration
VCC Trim Configuration | VBAT Supply & Mode | VCC Supply Level | Description
--- | --- | --- | ---
VCC target ≥ VBAT | - | VCC = VBAT | VCC supplied from VBAT
VCC target < VBAT | VBAT < 1.4 V | VCC = VCC target | VCC supplied through a low drop out regulator (LDO) from VBAT
VCC target < VBAT | VBAT > 1.4 V (LDO Mode) | VCC = VCC target | VCC supplied through a low drop out regulator (LDO) from VBAT
VCC target < VBAT | VBAT > 1.4 V (Buck Mode) | VCC = VCC target | VCC supplied through the DC-DC buck converter from VBAT

The internal LDO is used to reduce VCC to the specified target when VBAT exceeds the target VCC. For low noise operation (no switching DC-DC operation), or for low VBAT voltages where it make no sense to use a switching converter, configure VCC to LDO Mode by clearing the ACS_VCC_CTRL_BUCK_ENABLE bit from the ACS_VCC_CTRL register. In this mode, the RSL15 only uses VBAT or the internal LDO to supply VCC. An external VCC filtering capacitor is required in both modes. An external inductor is not required when using the LDO, as it is only used by the DC-DC converter when using the switching DC-DC operation.

The DC-DC converter is a buck converter used to reduce the battery voltage from a high value (from 1.4 to 3.6 V) to a lower VCC voltage value (from 1.0 to 1.32 V) with high efficiency. Do not enable the DC-DC converter when the supplied VBAT is 1.4 V or less. When the supplied VBAT exceeds 1.4 V, the DC-DC converter can be enabled by setting the ACS_VCC_CTRL_BUCK_ENABLE bit from the ACS_VCC_CTRL register. Setting this bit configures the VCC to select Buck Mode. Use of the DC-DC converter requires both an external VCC filtering capacitor and the DC-DC converter’s charge transferring inductor. In applications that only use the LDO Mode, the external inductor is not mandatory. For applications using a battery providing less than 1.4 V under any battery conditions, the recommendation is to only use the LDO Mode and not the Buck Mode.

The DC-DC buck converter periodically refreshes the flow of current through the external inductor to maintain the supply output. The refresh frequency for the buck converter is divided from SYSCLK using the CLK_DIV_CFG1_DCCLK_PRESCALE bit field from the CLK_DIV_CFG1 register. This prescaler provides a division of between 1 and 64 from SYSCLK, with a frequency defined by the following equation:

This clock needs to be configured for an update frequency of 4 MHz.

When the DC-DC converter is disabled, the CLK_DIV_CFG1_DCCLK_ENABLE bit-field from the CLK_DIV_CFG1 register can be used to disable DCCLK as well.

Other configurations provided by the ACS_VCC_CTRL register for VCC include:

| • | A Charge Control Mode setting (ACS_VCC_CTRL_CHARGE_CTRL). with a recommended default value of 1 (VCC_CONSTANT_IMAX). This setting selects between:

| ◦ | A Constant Current Mode where the output current is defined by the supplied VBAT voltage and trimmed VCC voltage. In this configuration, any output ripple on the VCC supply from the buck converter remains stable across VBAT input voltages, reducing the overall noise in the RSL15 system. This configuration can only be used if VBAT exceeds VCC by 0.2 V.

| ◦ | A Maximum Current Mode where the peak current transferred by the buck converter’s inductor is defined by a trim configuration (ACS_VCC_CTRL_ICH_TRIM) bit-field. If this mode is used, the maximum output from VCC is nominally limited to the current defined by the selected setting for an ideal inductor. In this mode, the output ripple increases as VBAT decreases towards VCC — which might cause additional noise within the RSL15 system. To limit charge current in the DC-DC converter, the default setting of 96 mA (maximum output of 48 mA) is recommended. If the power supervisory circuit is resetting the system when using the DC-DC converter in the user circuit and under the user application’s operating conditions, we recommend:

| ▪ | Using a higher setting than the default (up to the highest setting of 256 mA), or

| ▪ | Increasing the DCCLK frequency to reduce the amount of charge transfer that is required in each charge cycle. This recommendation is intended to improve the system stability, handling the kind of stability issues that can arise from high current consumption cases when combined with non-ideal inductor and board series resistance values.

NOTE: Custom calibration settings for ICH_TRIM can be stored to NVR6, as described in the RSL15 Firmware Reference Resource Usage table. If available, these values are loaded by the sample code provided in the SDK.

| • | A pulse control (ACS_VCC_CTRL_PULSE_CTRL) bit that can be used to enable a self-clocking mode. By default, the DC-DC converter is set to Single-Pulse Mode, where it is clocked with each pulse of a divided clock that is pre-scaled from SYSCLK using the CLK_DIV_CFG1_DCCLK_PRESCALE bit-field from the CLK_DIV_CFG1 register. In Multi-Pulse Mode, the DC-DC converter operates in a self-clocking mode that continuously charges and discharges the DC-DC inductor until VCC reaches its trimmed level. Multi-Pulse Mode is recommended only for cases where SYSCLK is below the desired DCCLK frequency, as this results in increased DC-DC current consumption.

| • | To support high-current use cases, a Continuous Conduction Mode has been provided that can be enabled using the ACS_VCC_CTRL_CCM_ENABLE bit. In this mode, the DC-DC converter continually operates to allow support for higher current loads. As use of this mode increases the power consumption of the RSL15 system, we recommend not using this mode for most use cases.

The converter has the following additional features:

| • | An activated output signal, which is high while the converter is in a charging/discharging cycle. This signal can be used to measure the converter output current but can only be monitored via the AOUT multiplexed output feature; see General Purpose Input/Output for more information.

| • | An overload output signal, which is set high if the peak inductor current goes above about 300 mA. This signal can be used to detect inductor saturation. When enabled through the ACS_WAKEUP_CFG_DCDC_OVERLOAD_EN control, the overload detection also generates a wakeup signal in Low Power Mode and interrupts the core, and the block automatically switches to LDO Mode. The corresponding ACS_WAKEUP_CTRL_DCDC_OVERLOAD_WAKEUP flag must be cleared to disable LDO Mode.

| • | In Sleep Mode, the DC-DC converter is not shut down, but regulates its output voltage to a lower level. Selection of Buck Mode or LDO Mode works the same way as it does in Run Mode. As the quiescent current of the Buck Mode is very low, the current savings are significant even for loads below 100 nA.

### Internal Bandgap Reference Voltages

The bandgap block provides a 0.75 V reference voltage, stabilized over temperature and process variations by the regulators. This voltage is soft programmable in steps of 2.5 mV from a nominal voltage of 0.67 to 0.825 V. This block also provides the bias current for all analog blocks, except for the digital supply and POR blocks.

This reference voltage is calibrated and stored in NVR7 during device production, and use of this calibrated setting is recommended for all use cases and most operating conditions. The ROM loads and uses the calibrated bandgap trim setting for 0.75 V from NVR7.

IMPORTANT: The bandgap reference voltage increases at the extreme temperatures of the operating range. If there is an increase in the bandgap reference voltage, the system typically experiences an increased system current consumption. To reduce this impact for devices that are continuously operating at a temperature extreme (below -30 °C and above +70 °C), the bandgap can be re-calibrated while operating at the temperature extreme. If at any point the device is no longer operating at an extreme temperature, we recommend reverting back to the calibrated setting stored in NVR7.

ACS_BG_CTRL is the bandgap control register, whose bits can be set for various functions. The ACS_BG_CTRL_SLOPE_TRIM bit field controls the degree to which trimming depends on the temperature coefficient, and the ACS_BG_CTRL_VTRIM bit field configures reference voltage trimming in 2.5 mV steps.

### RF Supply Voltage

The RF front-end is supplied by the RF supply voltage (VDDRF). This supply voltage can be supplemented by the RF power amplifier supply voltage (VDDPA), if the TX power required by a user application exceeds the available TX power levels possible from VDDRF.

The VDDRF block is used to provide a regulated voltage, trimmable from a nominal voltage of 0.75 to 1.38 V in 10 mV steps, from the VCC supply. This voltage is used to supply the radio front-end, which requires a high current.

CAUTION: VDDRF must not exceed 1.32 V, or damage to the device can occur.

NOTE: The VDDRF pin can be driven by an external voltage regulator when the regulator is disabled. To disable VDDRF, clear the ACS_VDDRF_CTRL_ENABLE bit from the ACS_VDDRF_CTRL register.

This supply is typically trimmed to a level that supplies the TX power amplifier with appropriate TX power for the user application’s use case. If the TX power amplifier requires a supply at a level exceeding VCC, the VDDPA separately powers the TX power amplifier, and the VDDRF supply needs to be trimmed to the lowest available calibrated setting that provides the desired RX sensitivity. The "Voltage Supply Values and Target Voltages" table shows the image supply values for achieving certain TX power levels.

Table: Voltage Supply Values and Target Voltages
TX Power (dBm) | Source | Target Voltage (V)
--- | --- | ---
0 | VDDRF | 1.10
1 | VDDRF or VDDPA (low VCC cases) | 1.15
2 | VDDRF or VDDPA (low VCC cases) | 1.20
3 | VDDPA | 1.29
4 | VDDPA | 1.39
5 | VDDPA | 1.52
6 | VDDPA | 1.66

In the ACS_VDDRF_CTRL register, the ACS_VDDRF_CTRL_READY bit configures whether the supply voltage is in Ready Mode. The ACS_VDDRF_CTRL_CLAMP bit controls the output in Disable Mode — it can be used to send the output HIZ or clamp the output to ground. The ACS_VDDRF_CTRL_ENABLE bit enables or disables the VDDRF regulator. The ACS_VDDRF_CTRL_VTRIM bit field controls configuration of the output voltage trimming in 10 mV steps. We recommend that some margin from VCC be kept, in order to ensure correct performance. This margin is typically 50 mV. For example, if VCC is set to 1.2 V, VDDRF ought to be set no higher than 1.15 V.

### VDDPA

VDDPA is an optional RF TX power ampl ifier supply voltage. This block is used to provide a regulated voltage, trimmable from a nominal voltage of 1.1 to 1.7 V in 10 mV steps, from the VDDA voltage (charge pump). This voltage is used to supply the TX power amplifier block of the radio, whenever this block requires a supply voltage that exceeds the level of VCC to achieve the desired TX output power. To enable VDDPA, set the ACS_VDDPA_CTRL_ENABLE bit from the ACS_VDDPA_CTRL register.

#### Connecting and Using VDDPA

When using the VDDPA regulator, care must be taken to ensure that VDDPA and VDDRF are connected in such a way that conflicts between the two supplies cannot result, thus avoiding damage to the device. The connections between VDDRF, VDDPA and the RF front-end (including the RF front end's power amplifier) are shown in VDDRF and VDDPA powering the RFFE (figure).

Figure: VDDRF and VDDPA powering the RFFE

When VDDPA is enabled (or in Dynamic Mode — see Dynamic VDDPA Control), the ACS_VDDPA_CTRL_VDDPA_SW_CTRL bit must be reset, to set the switch in High Impedance Mode (which connects VDDPA to the RF power amplifier, if enabled). When using only VDDRF to power the RF power amplifier (VDDPA is disabled), close the switch by setting the VDDPA_CTRL_VDDPA_SW_CTRL bit.

#### Dynamic VDDPA Control

The RSL15 system is a dynamic VDDPA feature. The VDDPA dynamic control is enabled by setting the SYSCTRL_VDDPA_CFG0_DYNAMIC_CTRL bit in the SYSCTRL_VDDPA_CFG0 register. VDDPA itself must be disabled in order for the dynamic VDDPA feature to work correctly. If the VDDPA is enabled, it stays on consistently, bypassing the dynamic control feature. The purpose of the mechanism is twofold:

| • | To dynamically enable the VDDPA regulator during TX operations and keep it disabled otherwise, in order to minimize the power consumption. The mechanism automatically controls the enabling/switching of the VDDPA regulator when the ACS_VDDPA_CTRL_VDDPA_ENABLE bit is reset and the ACS_VDDPA_CTRL_VDDPA_SW_CTRL bit is set, both in the ACS_VDDPA_CTRL register.

| • | To mitigate possible out-of-band issues by applying a progressive voltage ramp up/down on the VDDPA regulator supplying the RF front-end power amplifier (PA). The mechanism dynamically controls the VDDPA voltage in the range specified by the ACS_VDDPA_CTRL_VDDPA_INITIAL_VTRIM and ACS_VDDPA_CTRL_VDDPA_VTRIM fields of the ACS_VDDPA_CTRL register.

The different voltage ramp up/down steps need to be properly synchronized with the RF front-end TX operations, as illustrated in the "Timing Diagram of the Dynamic VDDPA Operation" figure. All of the time durations and time delays mentioned in the figure are specified in system clock cycles.

Figure: Timing Diagram of the Dynamic VDDPA Operation

When dynamic VDDPA control is enabled, the ramp up is characterized by several parameters that can be configured in SYSCTRL_VDDPA_CFG0 and SYSCTRL_VDDPA_CFG1.

SYSCTRL_VDDPA_CFG0_SW_CTRL_DELAY

This setting controls the delay before the power source for the RF power amplifier switches from VDDRF to VDDPA, once an RF transmission has been initiated. It is configured in the SYSCTRL_VDDPA_CFG0 register.

SYSCTRL_VDDPA_CFG0_RAMPUP_DELAY

This setting controls the delay before the VDDPA voltage ramp begins, once an RF transmission has been initiated. It is configured in the SYSCTRL_VDDPA_CFG0 register.

SYSCTRL_VDDPA_CFG1_RAMPUP_TIME

This setting is a multiplication of the values in the SYSCTRL_VDDPA_CFG1_RAMPUP_STEP and SYSCTRL_VDDPA_CFG1_RAMPUP_STEP_TIME bit fields from the SYSCTRL_VDDPA_CFG1 register. It represents the total time taken to ramp the VDDPA voltage from the value of the ACS_VDDPA_CTRL_INITIAL_VTRIM field up to the value of the ACS_VDDPA_CTRL_VTRIM setting in the same register.

SYSCTRL_VDDPA_CFG1_VDDPA_VOLTAGE

This setting is controlled by the ACS_VDDPA_CTRL_VTRIM field of the ACS_VDDPA_CTRL register. It is the final voltage that the VDDPA regulator reaches after the time value found in the SYSCTRL_VDDPA_CFG1_RAMPUP_TIME field of the SYSCTRL_VDDPA_CFG1 register. This voltage is used to supply the RF power amplifier during the actual RF transmission.

SYSCTRL_VDDPA_CFG1_RAMPDOWN_TIME

This setting is a multiplication of the values in the SYSCTRL_VDDPA_CFG1_RAMPDOWN_STEP and SYSCTRL_VDDPA_CFG1_RAMPDOWN_STEP_TIME fields from the SYSCTRL_VDDPA_CFG1 register. It represents the total time taken to ramp the VDDPA voltage down from the nominal trim setting (the value of the ACS_VDDPA_CTRL_TRIM field in the ACS_VDDPA_CTRL) to the initial trm setting (the value of the ACS_VDDPA_CTRL_INITIAL_VTRIM field in the same register).

SYSCTRL_VDDPA_CFG0_DISABLE_DELAY

This setting controls the total delay from the end of the time value in the SYSCTRL_VDDPA_CFG0_RAMPDOWN_TIME field of the SYSCTRL_VDDPA_CFG0 register, at which point the VDDPA is back to the voltage level value in the ACS_VDDPA_CTRL_INITIAL_VTRIM field from the ACS_VDDPA_CTRL register, to the point at which the dynamic VDDPA control ends and the RF power amplifier is switched back over to VDDRF (one cycle after VDDPA is disabled). This delay is configured in SYSCTRL_VDDPA_CFG0.

In order to avoid unexpected behavior, we recommend that you have the VDDPA initial trim value (in the ACS_VDDPA_CTRL_INITIAL_VTRIM field from the ACS_VDDPA_CTRL register) as close to the value of the ACS_VDDRF_CTRL_VTRIM bit from the ACS_VDDRF_CTRL register as possible, and that you only enable or disable dynamic VDDPA control when the VDDPA is disabled and the radio is idle.

### Digital Supply Voltages

The RSL15 SoC includes internally regulated digital supply voltages, for which the calibrated settings are strongly recommended:

| • | VDDC is the core digital voltage that is used for most of the RSL15 system’s digital components.

| • | VDDCRET replaces VDDC in power modes that use state retention of the RSL15 system’s digital components.

| • | VDDM is the memory digital voltage that is used for the ROM and RAM memories in the RSL15 system, as well as the connections between the core and flash/GPIOs.

| • | VDDMRET replaces VDDM in power modes that use state retention of memories and memory-mapped elements of the RSL15 system.

| • | VDDT is the supply for the baseband timer used in Low Power Modes. When VDDT is enabled (by the ACS_VDDRET_CTRL_VDDTRET_EN bit from the ACS_VDDRET_CTRL register), the VDDT power switch connects VDDT to VDDCRET (when the VDDTRET regulator is enabled) or VCCACS (otherwise).

This block is used twice to provide two regulated voltages derived from the VCC supply. These supplies are trimmable from a nominal voltage of 0.75 to 1.38 V in 10 mV steps. The default voltage at startup is controlled by the POR block and Program ROM, to ensure safe operation with an untrimmed bandgap. The user must not use a voltage higher than 1.32 V, as this can result in damage to the device.

CAUTION: Voltage must not exceed 1.32 V, as damage to the device can occur.

NOTE: For divide packages where VDDC and VDDM pads are accessible, the VDDC and VDDM supplies can also be driven by an external voltage regulator when the regulators are disabled.

In Run Mode, both VDDC and VDDACS (analog control subsystem) regulators’ outputs are shorted together. If VDDC is trimmed below 1.0 V for low frequency operating use cases, the VDDACS must also be trimmed lower. If this is not done, the VDDC level saturates to the VDDACS voltage.

The digital retention supply regulator is designed to consume less power, and to guarantee the retention of the state of digital blocks (VDDCRET) and the contents of memory (VDDMRET) to the extended supply limit.

The ACS_VDDC_CTRL and ACS_VDDM_CTRL registers contain bits with identical names and identical functions. The STANDBY_VTRIM bit controls the VDDC standby voltage trimming in 10 mV steps. The ENABLE_LOW_BIAS bit is used to specify whether the regulator biasing is normal or low. The SLEEP_CLAMP bit sets the output to HIZ or clamps the output to ground, in Sleep Mode. The VTRIM bit configures output voltage trimming in 10 mV steps in both ACS_VDDC_CTRL and ACS_VDDM_CTRL (for Run Mode).

The ACS_VDDRET_CTRL has three different bit fields used to trim each of the retention regulators. These are listed here:

| • | The ACS_VDDRET_CTRL_VDDCRET_VTRIM bit controls the VDDCRET retention regulator voltage trimming value, while ACS_VDDRET_CTRL_VDDCRET_ENABLE enables or disables the VDDCRET retention regulator.

| • | The ACS_VDDRET_CTRL_VDDMRET_VTRIM bit controls the VDDMRET retention regulator voltage trimming value. ACS_VDDRET_CTRL_VDDMRET_ENABLE enables or disables the VDDMRET retention regulator.

| • | The ACS_VDDRET_CTRL_VDDACSRET_VTRIM bit controls the VDDACS regulator voltage trimming value. ACS_VDDRET_CTRL_VDDTRET_ENABLE connects or disconnects VDDT to/from the VDDACS regulator.

### Analog Supply Voltage (VDDA)

The analog supply voltage makes use of an internal charge pump to generate a configurable regulated supply voltage. This voltage is used for all of the non-RF analog components. This supply uses a boost converter with an external capacitance between the CAP0 and CAP1 pads as part of its charge pump circuit, to effectively increase the system supply (VCC) voltage as required by these blocks.

The charge pump, VDDCP, is shorted to VDDA.

The charge pump has four different output power trimming modes to allow a better balance between consumption and power delivery. The default maximum current draw of the output power is 4 mA. If an application requires a heavy current draw on VDDA, the PTRIM[1:0] bit in the ACS_VDDCP_CTRL register can be configured to 0x3, to receive a maximum current of 16 mA.

The VDDA charge pump periodically refreshes its external capacitance to maintain the supply output. The refresh frequency for the charge pump is divided from SLOWCLK (see Slow Clock (SLOWCLK)) using the CLK_DIV_CFG1_CPCLK_PRESCALE bit field from the CLK_DIV_CFG1 register. This prescaler provides a division of between 1 and 64 from SLOWCLK, with a frequency defined by the following equation:

This clock needs to be configured for an update frequency between 10 kHz and 400 kHz, with no restrictions on the duty cycle of the source clock. When VDDA is disabled, the CLK_DIV_CFG1_CPCLK_ENABLE bit-field from the CLK_DIV_CFG1 register can be used to disable the charge pump clock as well.

The analog supply voltage is accessible at the VDDA pad for capacitive filtering.

The charge pump can stay active during Sleep Mode as long as the STANDBYCLK is active in Sleep Mode. To enable the charge pump before entering Sleep Mode, set the VDDCP_ENABLE bit in the ACS_SLEEP_MODE_CFG register. The frequency for the charge pump in Sleep Mode can be configured in the ACS_VDDCP_CTRL_CPCLK_FREQ field in the ACS_VDDCP_CTRL register, with the maximum setting being 32.768 kHz.

### Charge Pump Supply Voltage (VDDCP)

The VDDCP charge pump is clocked using CPCLK, which is divided from SYSCLK using the CLK_DIV_CFG1_CPCLK_PRESCALE bit-field from the CLK_DIV_CFG1 register.

IMPORTANT: Important: When VDDPA is enabled, the CPCLK frequency must be configured to a frequency other than 125 kHz for optimal RF performance (otherwise transmit modulation failures may occur).

### Flash Memory Supply Voltage

The VDDFLASH regulator is used to provide a regulated voltage from 0.75 to 2.3 V in 25 mV steps. The voltage can be adjusted using the ACS_VDDFLASH_CTRL_VTRIM field in the ACS_VDDFLASH_CTRL register. When the regulator is disabled, the output pin can also be driven by an external source, and the external VDDFLASH is in a high impedance state, allowing the external source to provide power. The regulator is enabled or disabled by the ACS_VDDFLASH_CTRL_ENABLE bit in the ACS_VDDFLASH_CTRL register. An external decoupling capacitor is required on the VDDFLASH pad. We highly recommended using the default 1.6 V setting for proper flash operation.

A current limiter can be enable to limit the maximum output current. Two current limit settings are available: one to reduce the short-circuit current to 70 mA, and a second one to reduce the inrush current during boot-up to 4 mA. The default setting is 4 mA and can be configured by the ACS_VDDFLASH_CTRL_SOFT_START bit from the ACS_VDDFLASH_CTRL register. The current limiter functionality can be configured by the ACS_VDDFLASH_CTRL_ENABLE_LIMITER bit from the same register.

The circuit has a comparator to indicate when the output voltage reaches 90% of the target value. This comparator feedback can be connected to the reset circuitry to assert a reset if necessary. This functionality can be enabled or disabled by the ACS_VDDFLASH_CTRL_MASK_READY bit from the ACS_VDDFLASH_CTRL register.