# Universal Asynchronous Receiver-Transmitter (UART) Interfaces

The general-purpose Universal Asynchronous Receiver-Transmitter (UART) interface provides support for communicating with devices that use standard UART and RS-232 transmission protocols.

The UART interface is multiplexed onto the GPIO pads. These can be configured for the UART interface's receiver and transmitter signals, with the necessary physical pad configuration (pull-up/pull-down resistor and low pass filtering configuration for the RX signal, and drive strength configuration for the TX signal). For more information about configuring the multiplexed GPIO functionality, see General Purpose Input/Output.

The UART interface can be enabled using the UART_CTRL_ENABLE bit or disabled using the UART_CTRL_DISABLE bit, both in the UART_CTRL register.

NOTE: When the UART_CTRL_DISABLE bit is set to 1, any ongoing transaction, TX or RX, is completed before disabling the interface, and the UART transmit line UART_TX is set high.

A reset can be performed on the UART interface by writing to the UART_CTRL_RESET bit in the UART_CTRL register. This causes the UART interface to be disabled, and the register values to be reset to their power-on defaults.

The UART interface operates in half- or full-duplex mode using a standard data format of one start bit, eight data bits, one stop bit, and no parity bits. All data bytes being sent or received are interpreted as starting with the LSB. The "UART Transaction Waveform" figure shows the waveform for a UART transmit or receive transaction.

Figure: UART Transaction Waveform

Data transmission is started by writing to the UART_TX_DATA register. Data that has been received over the UART interface is stored in the UART_RX_DATA register. The UART_TX_DATA and UART_RX_DATA registers are only accessible after the interface has been enabled via the UART_CTRL register.

The UART interface runs on UARTCLK, which is sourced from a scaled version of SYSCLK. UARTCLK is scaled by setting the UARTCLK_PRESCALE bits in the CLK_DIV_CFG0 register. Definitions for standard baud rates are provided for the UART_CFG_CNT_STEPbit field in the UART_CFG register.

IMPORTANT: For proper functionality, UART interfaces require both sides of a connection to have an absolute clock accuracy error of less than 2.5%. To allow for clock jitter, it is recommended that all UART communications use a clock with a maximum of 2% error versus the expected target frequency.

The baud rates (specified in bits per second) for the UART interfaces are defined in terms of the UARTCLK frequency and several configuration parameters, as seen in the following equation for baud rate calculation, with UARTCLK frequency in Hz:

For a UARTCLK frequency of 1 MHz, the baud rate is determined as follows:

For example, if a baud rate of 115200 bps is desired, the value of CNT_STEP must be set to 30198 for a UARTCLK frequency of 1 MHz, which results in an actual baud rate of 115203.587 bps.

Data transfers using the UART interface can be controlled by the host processor using a memory-mapped register interface and/or the DMA block. The UART_CFG_TX_DMA_ENABLE and UART_CFG_RX_DMA_ENABLE bits in the UART_CFG register determine which request, whether read or write, needs to be completed using the DMA block. Both RX/TX interrupts and RX/TX DMA requests can be generated concurrently; if DMA requests are used, the data transfer requested is fulfilled by the DMA before the interrupt service routine is executed. User applications that do not use DMA or interrupts can poll the UART_STATUS_TX_REQ and UART_STATUS_RX_REQ bits in the UART_STATUS register to control data transfers. When UART_STATUS_TX_REQ is set to 1, the application can write to the UART_TX_DATA register to send data over the UART interface. When a new byte has been received over the UART interface and written to the UART_RX_DATA register, UART_STATUS_RX_REQ is set to 1. To avoid loss of data, the application must read the received byte using the processor or DMA before the next byte is received; otherwise an overrun occurs, and the UART_STATUS_OVERRUN flag in the UART_STATUS register is set to 1.

## UART Interrupts

The UART interface uses three associated interrupts that separately control transmission of UART data, reception of UART data, and handling of UART transmission errors. See Nested Vector Interrupt Controller (NVIC) for information regarding interrupt configuration and handling interrupts for the Arm Cortex-M33 processor.

If a user application is transmitting data from the UART interface, the UART_TX interrupt indicates that data transmission can begin, and that the application can now load the first byte into the UART_TX_DATA register if this is the first interrupt, or load the next byte for subsequent interrupts. The next TX interrupt is generated as soon as the TX transmission has begun. To enable the UART_TX interrupt, set the UART_CFG_TX_INT_ENABLE bit in the UART_CFG register to 1.

If a user application is receiving data from the UART interface, the UART_RX interrupt indicates that a data byte has been successfully received and has been written to the UART_RX_DATA register. To enable the UART_RX interrupt, set the UART_CFG_RX_INT_ENABLE bit in the UART_CFG register to 1.

When using the DMA or the register interface to control data transfers over a UART interface, the UART_ERROR interrupt indicates that an overrun has occurred when data received from the UART interface has not been read by the DMA or processor before being overwritten. Detection of an overrun condition is enabled using the UART_CTRL_OVERRUN_INT_ENABLE bit in the UART_CTRL register. When this occurs, the UART_STATUS_OVERRUN_STATUS sticky bit from the UART_STATUS register is set. To clear it, write 1 to the UART_STATUS_OVERRUN_CLEAR bit.

NOTE: Once a value of 1 is written to the UART_STATUS_OVERRUN_CLEAR bit, it is automatically reset in the next clock cycle. Consequently, this bit is always read back as 0.

For registers, see UART Registers.