### SPI_CFG

Bit Field | Read/Write | Field Name | Description
--- | --- | --- | ---
23 | RW | TX_DMA_ENABLE | Enable/disable the TX DMA request
22 | RW | RX_DMA_ENABLE | Enable/disable the RX DMA request
21 | RW | TX_END_INT_ENABLE | Enable/disable the TX interrupt
20 | RW | TX_START_INT_ENABLE | Enable/disable the TX interrupt
19 | RW | RX_INT_ENABLE | Enable/disable the RX interrupt
18 | RW | CS_RISE_INT_ENABLE | Enable/disable the CS rise interrupt (slave mode only)
17 | RW | OVERRUN_INT_ENABLE | Enable/disable the overrun interrupt
16 | RW | UNDERRUN_INT_ENABLE | Enable/disable the underrun interrupt
14:13 | RW | MODE | Select the SPI master mode (ignored in slave mode)
12:8 | RW | WORD_SIZE | Select the SPI word size (word size = SPI_WORD_SIZE + 1)
7:4 | RW | PRESCALE | Prescale the SPI clock for master mode
2 | RW | CLK_PHASE | Select the SPI clock phase
1 | RW | CLK_POLARITY | Select the SPI clock polarity
0 | RW | SLAVE | Use the SPI interface as master or slave

Bit Field | Field Name | Value Symbol | Value Description | Hex Value
--- | --- | --- | --- | ---
23 | TX_DMA_ENABLE | SPI_TX_DMA_DISABLE | No TX DMA request is generated | 0x0*
|  | SPI_TX_DMA_ENABLE | A TX DMA request is generated when TX buffer is empty | 0x1
22 | RX_DMA_ENABLE | SPI_RX_DMA_DISABLE | No RX DMA request is generated | 0x0*
|  | SPI_RX_DMA_ENABLE | An RX DMA request is generated when RX buffer is full | 0x1
21 | TX_END_INT_ENABLE | SPI_TX_END_INT_DISABLE | No TX interrupt is raised | 0x0*
|  | SPI_TX_END_INT_ENABLE | A TX interrupt is raised when a TX data transmission is finished | 0x1
20 | TX_START_INT_ENABLE | SPI_TX_START_INT_DISABLE | No TX interrupt is raised | 0x0*
|  | SPI_TX_START_INT_ENABLE | A TX interrupt is raised when a new TX data send by the SPI interface is started | 0x1
19 | RX_INT_ENABLE | SPI_RX_INT_DISABLE | No RX interrupt is raised | 0x0*
|  | SPI_RX_INT_ENABLE | An RX interrupt is raised when new data is received by the SPI interface | 0x1
18 | CS_RISE_INT_ENABLE | SPI_CS_RISE_INT_DISABLE | No interrupt is raised when the CS rises in slave mode | 0x0*
|  | SPI_CS_RISE_INT_ENABLE | A common interrupt is raised when the CS rises in slave mode | 0x1
17 | OVERRUN_INT_ENABLE | SPI_OVERRUN_INT_DISABLE | No interrupt is raised when an overrun is detected | 0x0*
|  | SPI_OVERRUN_INT_ENABLE | A common interrupt is raised when an overrun occurs on the SPI interface | 0x1
16 | UNDERRUN_INT_ENABLE | SPI_UNDERRUN_INT_DISABLE | No interrupt is raised when an underrun is detected | 0x0*
|  | SPI_UNDERRUN_INT_ENABLE | A common interrupt is raised when an underrun occurs on the SPI interface | 0x1
14:13 | MODE | SPI_MODE_SPI | SPI normal mode (separate RX and TX data) | 0x0*
|  | SPI_MODE_DSPI | SPI dual mode (two bideractional data pins) | 0x1
|  | SPI_MODE_QSPI | SPI quad mode (four bidirectional data pins) | 0x2
12:8 | WORD_SIZE | SPI_WORD_SIZE_1 | SPI transfers use 1-bit words | 0x0*
|  | SPI_WORD_SIZE_4 | SPI transfers use 4-bit words | 0x3
|  | SPI_WORD_SIZE_8 | SPI transfers use 8-bit words | 0x7
|  | SPI_WORD_SIZE_16 | SPI transfers use 16-bit words | 0xF
|  | SPI_WORD_SIZE_24 | SPI transfers use 24-bit words | 0x17
|  | SPI_WORD_SIZE_32 | SPI transfers use 32-bit words | 0x1F
7:4 | PRESCALE | SPI_PRESCALE_2 | Prescale the SPI interface clock by 2 | 0x0*
|  | SPI_PRESCALE_4 | Prescale the SPI interface clock by 4 | 0x1
|  | SPI_PRESCALE_8 | Prescale the SPI interface clock by 8 | 0x2
|  | SPI_PRESCALE_16 | Prescale the SPI interface clock by 16 | 0x3
|  | SPI_PRESCALE_32 | Prescale the SPI interface clock by 32 | 0x4
|  | SPI_PRESCALE_64 | Prescale the SPI interface clock by 64 | 0x5
|  | SPI_PRESCALE_128 | Prescale the SPI interface clock by 128 | 0x6
|  | SPI_PRESCALE_256 | Prescale the SPI interface clock by 256 | 0x7
|  | SPI_PRESCALE_512 | Prescale the SPI interface clock by 512 | 0x8
|  | SPI_PRESCALE_1024 | Prescale the SPI interface clock by 1024 | 0x9
2 | CLK_PHASE | SPI_CLK_PHASE_RISING | In both master and slave modes SERO changes on the falling edge of the SPI clock. The SERI is sampled at the rising edge of the SPI clock | 0x0*
|  | SPI_CLK_PHASE_FALLING | In both master and slave modes SERO changes on the rising edge of the SPI clock. The SERI is sampled at the falling edge of the SPI clock | 0x1
1 | CLK_POLARITY | SPI_CLK_POLARITY_NORMAL | In Master mode in idle state the spi clock polarity is low | 0x0*
|  | SPI_CLK_POLARITY_INVERSE | In Master mode in idle state the spi clock polarity is high | 0x1
0 | SLAVE | SPI_SELECT_MASTER | Use the SPI interface in master mode | 0x0*
|  | SPI_SELECT_SLAVE | Use the SPI interface in slave mode | 0x1