### SPI_CTRL

Bit Field | Read/Write | Field Name | Description
--- | --- | --- | ---
19 | R | CS_STATUS | SPI CS status
18:17 | R | MODE_STATUS | SPI mode status
16 | R | ENABLE_STATUS | SPI enable status
9 | W | CS_0 | Lower the SPI chip-select line (master mode)
8 | W | CS_1 | Raise the SPI chip-select line (master mode)
7 | W | MODE_NOP | Set mode to no operation
6 | W | MODE_WRITE | Set mode to read operation
5 | W | MODE_READ | Set mode to write operation
4 | W | MODE_READ_WRITE | Set mode to read and write operation
3 | W | START | Start a data transfer in master read mode
2 | W | RESET | Reset the SPI interface
1 | W | DISABLE | Disable the SPI interface
0 | W | ENABLE | Enable the SPI interface

Bit Field | Field Name | Value Symbol | Value Description | Hex Value
--- | --- | --- | --- | ---
19 | CS_STATUS | SPI_STATUS_CS_0 | SPI CS is low | 0x0
|  | SPI_STATUS_CS_1 | SPI CS is high | 0x1*
18:17 | MODE_STATUS | SPI_STATUS_MODE_NOP | Mode is no operation (not allowed in DSPI and QSPI modes) | 0x0*
|  | SPI_STATUS_MODE_WRITE | Mode is write data | 0x1
|  | SPI_STATUS_MODE_READ | Mode is read data | 0x2
|  | SPI_STATUS_MODE_READ_WRITE | Mode is read and write data (not allowed in DSPI and QSPI modes) | 0x3
16 | ENABLE_STATUS | SPI_STATUS_DISABLED | SPI interface is disabled | 0x0*
|  | SPI_STATUS_ENABLED | SPI interface is enabled | 0x1
9 | CS_0 | SPI_CS_0 | Set the SPI CS signal low | 0x1
8 | CS_1 | SPI_CS_1 | Set the SPI CS signal high | 0x1
7 | MODE_NOP | SPI_MODE_NOP | Set the mode to no operation | 0x1
6 | MODE_WRITE | SPI_MODE_WRITE | Set the mode to write operation | 0x1
5 | MODE_READ | SPI_MODE_READ | Set the mode to read operation | 0x1
4 | MODE_READ_WRITE | SPI_MODE_READ_WRITE | Set the mode to read and write operation (not allowed in DSPI and QSPI modes) | 0x1
3 | START | SPI_START_READ | Start a transfer on the SPI interface (master read mode only) | 0x1
2 | RESET | SPI_RESET | Reset the SPI interface | 0x1
1 | DISABLE | SPI_DISABLE | Disable the SPI interface | 0x1
0 | ENABLE | SPI_ENABLE | Enable the SPI interface | 0x1