## System Control

The Arm Cortex-M33 processor is supported by a system control block (SCB) that supports configuration information and functionality defined by the RSL15 implementation. This includes configuration of:

ICB_ICTR

The Interrupt Controller Type register (also referred to as the SCB_ICTR register), which indicates the number of interrupts supported by the NVIC. RSL15 uses 57 external interrupts (NVIC_INTLINESNUM_33_64, hex value 0x1)

SCB_CPUID

The CPU ID base register, containing the version of the Arm Cortex-M33 processor used in RSL15

SCB_ICSR

The Interrupt Control and State register, containing system state information

SCB_VTOR

The Vector Table Offset register, containing a pointer to the active vector table; this register is banked, with separate copies maintained by the system for both secure and non-secure execution.

SCB_AIRCR, SCB_SHPR*

The Application Interrupt and Reset Control register, used to configure the NVIC priority configuration (as described in Nested Vector Interrupt Controller (NVIC)), to clear all active interrupts, and to apply requests for a software reset of the device. This register pairs with the System Handler Priority registers, which set the equivalent priority settings for system interrupts and exceptions.

SCB_SCR

The System Control register, used to configure the Arm Cortex-M33 core sleep behaviors

SCB_CCR

The Configuration Control register, used to configure other Arm Cortex-M33 core behaviors

SCB_CFSR, SCB_HFSR, SCB_DFSR, SCB_MMFAR, SCB_BFAR

The fault status and address registers, used for handling exceptions encountered by the Arm Cortex-M33 processor

SCB_NSACR

Non-Secure Access Control register, used to configure whether the floating point extension can be available to an application using a non-secure execution state.

For more information about the SCB, refer to the Arm v8-M Architecture Reference Manual and the Arm Cortex-M33 Processor Technical Reference Manual.