# Debug Port

All applications executing on the Arm Cortex-M33 processor can be debugged through the SWJ-DP, which can be configured to either serial wire or JTAG debug port communications. The SWJ-DP provides access to all of the Arm Cortex-M33 processor registers, and to the memory available through the memory buses attached to the Arm Cortex-M33 processor. This transparent view of the system enables a user to review the current state of the system components through their associated memory-mapped control registers, and use this information to troubleshoot most issues in an application.

IMPORTANT: When operating in energy harvesting mode, full access to the system is available through the debug port. In other life cycles states, access to the device is restricted and controlled by debug certificates. For more information, see Arm TrustZone CryptoCell-312 Security IP.

IMPORTANT: When a debug port connection has been established, the debug port link remains active in low power modes if the Arm Cortex-M33-Debug power domain is not explicitly disabled. This supports debugging the functionality of an application that uses low power modes across a low power mode-wakeup cycle. For more information, see Keeping the Debugger Connected in Low Power Modes.

The SWJ-DP is assigned to two dedicated pads (JTCK, JTMS), which can be used as the debug port in serial wire (SW) mode. These two pads are augmented for JTAG mode using GPIOs 2 and 3 when the interface is used as a 4-wire JTAG interface, and optionally by GPIO 4 if the interface is used as a 5-wire JTAG interface. By default, GPIOs 2 through 4 are assigned to the SWJ-DP and must be deselected if a user wishes to reassign the GPIOs to other functionality. For more information about the functional configuration of GPIOs for this mode, see Functional Configuration.

When the SWJ-DP is used in serial wire mode, data is transferred using a single clock and single data signal. This interface mode is useful when the number of signals needed to form a debug port connection needs to be limited, but it is only half-duplex and has a relatively high overhead for transferring data.

When using the SWJ-DP in JTAG mode, data is transferred using a data control line, a pair of data lines, a clock, and an optional reset signal. This interface mode is useful when the number of signals used to form the debug port connection is not limited, and a higher throughput is required, as JTAG mode uses less data overhead than serial wire mode for full-duplex transfers.

To configure the GPIOs to support the SWJ-DP interface in JTAG mode, take the following steps before configuring the interface for JTAG mode:

- The JTAG test-reset signal (JNTRST) can be connected to GPIO 4 by setting the GPIO_JTAG_SW_PAD_CFG_CM33_JTAG_TRST_EN bit from the GPIO_JTAG_SW_PAD_CFG register; this is only required when using the SWJ-DP as a 5-pin JTAG interface.
- The JTAG data signals can be connected to GPIOs 2 (JTDI) and 3 (JTDO) by setting the GPIO_JTAG_SW_PAD_CFG_CM33_JTAG_DATA_EN bit from the GPIO_JTAG_SW_PAD_CFG register; this is required if you are using the SWJ-DP as a 4-pin or 5-pin JTAG interface.

To switch the SWJ-DP into JTAG mode, follow this initialization sequence:

1. Send at least 50 clock cycles on SWCLK with the SWDIO pad held high. This ensures that the current interface is in its reset state.
2. Use SWCLK to send 0xE73C (transmitted LSB first) using SWDIO. This initialization pattern switches the debug port to JTAG mode.
3. Send at least 5 clock cycles on SWCLK with SWDIO HIGH. This ensures that the JTAG interface enters its test-logic reset state.

To switch the SWJ-DP into serial wire mode, follow this initialization sequence:

1. Send at least 50 clock cycles on SWCLK with the SWDIO pad held high. This ensures that the current interface is in its reset state.
2. Use SWCLK to send 0xE79E (transmitted LSB first) using SWDIO. This initialization pattern switches the debug port to serial wire mode.
3. Send at least 50 clock cycles on SWCLK with SWDIO HIGH. This ensures that the serial wire interface enters its line reset state.

The pads that form the SWJ-DP interface support a limited degree of physical configuration. The output pads support a configurable drive strength, and the input pads support configurable pull-up resistances. Configuration of these interface pads uses the GPIO_JTAG_SW_PAD_CFG register. The physical configuration parameters are set as follows:

- JTMS (SWDIO) pad configuration:
  - A pull-up or pull-down resistor can be configured and applied to the pad using the GPIO_JTAG_SW_PAD_CFG_JTMS_PULL bit-field in the GPIO_JTAG_SW_PAD_CFG register.
  - The drive strength can be configured using the GPIO_JTAG_SW_PAD_CFG_JTMS_DRIVE bit-field in the same register.
  - A low-pass filter can be enabled or disabled using the GPIO_JTAG_SW_PAD_CFG_JTMS_LPF bit in the same register.
- JTCK (SWCLK) pad configuration:
  - A pull-up or pull-down resistor can be configured and applied to the pad using the GPIO_JTAG_SW_PAD_CFG_JTCK_PULL bit-field in the GPIO_JTAG_SW_PAD_CFG register.
  - A low-pass filter can be enabled or disabled using the GPIO_JTAG_SW_PAD_CFG_JTCK_LPF bit in the same register.
- Physical configurations of the GPIOs are used even when those pads are configured for use as part of the JTAG interface

The debug port provides external access to the standard Arm Cortex-M33 core debug controller that is on the private peripheral bus. For more information about the debug controller, see Debug Controller.