# SAR-ADC

## Power Source

The SAR-ADC — successive approximation analog-to-digital converter — can be supplied by VBAT or via the DIO9, and the differential inputs are configurable via the SENSOR_SAR_CFG register.

If DIO9 is used as the SAR supply source, the DIO_CFG[9].IO_MODE field must be set to DIO_MODE_DISABLE.

## Functional Description

The SAR-ADC is based on a standard successive approximation search algorithm. Its core blocks are shown in SAR-ADC Block Diagram (figure): capacitive DAC, comparator, and digital control.

A conversion starts by sampling the input voltage on the capacitors in the capacitive DAC. The digital control then steps through the DAC codes, starting at the MSB (largest DAC element). The comparator indicates whether the digital control code is higher or lower than the sampled signal.

The SAR-ADC is clocked using SENSOR_CLK, which is configured as described in Clock Source Configuration.

The input of the SAR-ADC is differential.

## Block Diagram

The "SAR-ADC Block Diagram" figure shows the internal structure of the SAR-ADC converter.

Figure: SAR-ADC Block Diagram

To allow for smaller, faster, and lower power analog operation, the calibrated 12-bit SAR-ADC is modified from the standard approach in several ways. First, the DAC capacitors are sized smaller than is necessary for 12-bit accuracy. Only the lowest 7 bits are sized for inherent matching. To achieve 12-bit performance, the upper five bits are implemented with six DAC elements. The sizes of these six elements ensure that with mismatch there are no dead areas in the ADC output. As a result, these elements are not binarily scaled, and the DAC code does not match the ADC output code. To create a 12-bit accurate ADC code, the digital block sums the weight values of the Capacitive DAC elements. The "Typical DAC Element Weights" table shows the typical DAC element weights.

Table: Typical DAC Element Weights
Bit | Weight | Component
--- | --- | ---
0 | 1 | Normally only for calibration
1 | 2 | Normally only for calibration
2 | 4 |
3 | 8 |
4 | 16 |
5 | 32 |
6 | 64 |
7 | 128 |
8 | 256 |
9 | 384 | Calibrated
10 | 704 | Calibrated
11 | 1280 | Calibrated
12 | 2304 | Calibrated
13 | 4096 | Calibrated
14 | 7105 | Calibrated
Total | 16384 |

The nine LSBs are binarily scaled, and their weights are fixed. The weights for the six MSBs are a function of matching, and vary from chip to chip. Once these values are determined, the ADC output is constructed from the final SAR DAC code and the weights as:

The minimum (unsigned) output code is 0, and, based on the weights in Typical DAC Element Weights (table), the maximum output code is 16384, the sum of all weights. The ADC output code requires 15 bits to represent the full range of the ADC.

## ADC Calibration

The accuracy of the final output code of the ADC is dependent on the accuracy of the element weights. As noted previously, the weights for the six largest DAC elements vary from chip to chip. A calibration routine is required to determine the correct weights for these elements. This calibration routine is built into the digital control block of the ADC. It measures the proper weight code for each of the six MSB elements eight times. The average of the eight measurements with two additional sub bits is used as the final weight value. The calibration routine requires 650 clock cycles to complete, and must be performed when the ADC reference voltages are settled and with input voltages around mid range. Subsequent changes in supply voltage and reference voltages do not require re-calibration. This allows the calibration to be run once after the system is powered up.

## ADC Outputs

SAR-ADC outputs are provided as a fraction of the selected supply range (as defined by the power supply reference).

- The output code can be selected to signed or unsigned (see the OUT_SEL configuration in SAR-ADC Registers).
  - In unsigned mode the output ranges typically from 0 to 16384.
  - In signed mode the output ranges typically from -8192 to 8192.
- In either case (signed or unsigned), the output code can exceed the minimum and maximum values, depending on the calibrated offsets and weights. No saturation is performed inside the block to minimize the gate count. But as the output has one guard MSB bit, there is no risk of result misinterpretation.
- Scaling: the ADC output code is a 15-bit bus. This allows the code to include the effects of the weight sub-bits. The 13 MSBs of the output code can be used to confine the output to 13 bits. If a 12-bit output is needed, additional saturation needs to be implemented to discard the MSB.
- Internal offset: the comparator in the ADC adds a DC offset to the output code. The current ADC design compensates this offset during the calibration process. When the offset is compensated, the result is an output code which is in the middle of the range when the analog inputs are set to the same voltage — — by register configuration.
- Auto zeroing: another offset compensation method allows compensating external circuits inaccuracies (such as external offset, unbalanced reference voltages, etc.). To measure this offset, the analog inputs have to be set by register configuration to and a conversion started in auto zeroing mode. The result of this conversion is registered and subtracted from subsequent conversions.

A certain number of clock cycles are needed for conversion of each sample, as follows:

- If the SENSOR_SAR_CTRL_MODE field of the SENSOR_SAR_CTRL register = SAR_CONV_12BIT (value 0x0, which is the default), conversion takes 14 clock cycles.
- If the SENSOR_SAR_CTRL_MODE field of the SENSOR_SAR_CTRL register = SAR_CONV_14BIT (value 0x1), conversion takes 16 clock cycles.

## Timing Diagrams

The following diagrams illustrate SAR-ADC timing for two different modes. The "Calibration and One Shot Conversion Mode" figure shows timing for the calibration and one shot conversion mode, while the "Continuous Conversion Mode (Mode = 0x0 or 0x1)" figure illustrates continuous conversion mode timing.

Figure: Calibration and One Shot Conversion Mode

Figure: Continuous Conversion Mode (Mode = 0x0 or 0x1)

For registers, see SAR-ADC Registers.