## Debug Controller

Access to the debug controller that underlies the debug port is restricted in many of the security lifecycle states. For more information, see Arm TrustZone CryptoCell-312 Security IP.

### Halting Debug Configuration and Status

The Debug Halting Control and Status Register (DHCSR) provides status information on the processor state, enables core debugging, and allows an external system to halt and single-step the core. To write to this register, DEBUG_HALT_KEY must be written to the CoreDebug_DHCSR_DBGKEY bit field.

The DHCSR is used to configure the Arm Cortex-M33 processor for halting debug. To enable halting debug, set the CoreDebug_DHCSR_C_DEBUGEN bit. If halting debug is enabled:

- To halt the core, set the CoreDebug_DHCSR_C_HALT bit.
- To single-step the core, set the CoreDebug_DHCSR_C_STEP bit.
- To mask interrupts while single-stepping, set the CoreDebug_DHCSR_C_MASKINTS bit (the core must be halted to write to this bit).
- To break a stalled memory access, where the memory access might be stalled due to a memory conflict with another component of the RSL15 system, set the CoreDebug_DHCSR_C_SNAPALL bit.

The Debug Exception and Monitor Control Register (DEMCR) contains a number of possible exception conditions that the debug tools might want to monitor during debug. When enabled, each of these vector catch configuration bits monitors for the specified fault or reset event. When a fault or event that is being monitored is detected, a core halt request is used to halt the core as soon as the currently executing instruction completes. Supported vector catch events include debug traps that trigger on:

- A core reset
- A memory management fault
- A bus fault
- Usage faults for:
  - No coprocessor errors
  - Unaligned accesses or division by 0
  - State errors
- A secure fault
- Errors when handling an interrupt or exception
- A Hard Fault

The DHCSR also provides a variety of debug-related status information, including:

- Whether the core has been reset or is resetting (CoreDebug_DHCSR_S_RESET_ST); this bit is cleared when read
- Whether an instruction has completed execution since this register has been last read; this bit is cleared when read
- Whether the core is in a locked state
- Whether the core is in Sleep Mode
- Whether the core has been halted
- Whether the most recent register read/write has completed; for more information, see Arm Cortex-M33 Processor Core Register Access.

NOTE: The DHCSR and all DEMCR bits that are not related to the debug monitor are only reset if a POR or similar event occurs. These registers are not reset for a core reset. For more information about resets, see Resets.

CAUTION: We strongly recommend that only the debugger use the DHCSR, because accesses to this register from application code can interfere with the debug behavior of the Arm Cortex-M33 processor debug port.

### Debug Monitor Configuration

The NVIC from the Arm Cortex-M33 processor contains a debug monitor that can be used to control debug activities. The debug monitor is tied to the debug monitor system interrupt (vector number 12) and is configured using the DEMCR register. To enable the debug monitor and debug monitor exception, set the CoreDebug_DEMCR_MON_EN bit from the DEMCR register. To manually pend the debug monitor exception, set the CoreDebug_DEMCR_MON_PEND bit from the DEMCR register. To single-step the core using the debug monitor (if the debug monitor is enabled), set the CoreDebug_DEMCR_MON_STEP bit from the DEMCR register.

The CoreDebug_DEMCR_MON_REQ bit from the DEMCR register indicates whether a debug monitor event has been caused by a manual request or a debug event (including a debug trap).

### Arm Cortex-M33 Processor Core Register Access

The Arm Cortex-M33 processor’s debug port includes a pair of registers that the debug port uses to provide read and write access to the Arm Cortex-M33 processor’s core registers: the Debug Core Register Selector Register (DCRSR) and the Debug Core Register Data Register (DCRDR). The DCRSR contains the selection of the register to be read from or written to, and the type of access used. To define the read/write direction, write REGWNR_READ or REGWNR_WRITE to the CoreDebug_DCRSR_REGWnR bit field. To set the register to be read, use the REGSEL_* bit settings for the CoreDebug_DCRSR_REGSEL bit field from the DCRSR.

Data written using the DCRSR is copied from the DCRDR to the specified core register. Similarly, data read using the DCRSR is written to the DCRDR, where it can be accessed using debug port memory reads. If the selector register selects the core special registers, the data read or written is interpreted using the bit fields described in the "Debug Core Register Data Register Special Register Mapping" table.

Table: Debug Core Register Data Register Special Register Mapping
Bit Field | Arm Cortex-M33 Processor Register
--- | ---
31:24 | CONTROL
23:16 | FAULTMASK
15:8 | BASEPRI
7:0 | PRIMASK

### Debug Fault Status Register

The Debug Fault Status register (DFSR) is used to monitor debug events, including:

- External debug requests
- Vector catches
- Data watchpoint matches
- BKPT instruction execution
- Halt requests

Each flag in the Debug Fault Status register is set independently when its debug condition occurs. The bits in this register are not set unless the event is caught. One of four things occurs if an event is detected:

If halting debug is enabled

Debug events stop the processor by going into debug mode.

If halting debug is disabled and the debug monitor is enabled

Debug events trigger a debug monitor handler call, if priority permits.

If halting debug and the debug monitor are both disabled

Some debug events are interpreted as Hard Faults, setting the SCB_HFSR_DBGEVT bit in the Hard Fault Status register. This always includes BKPT events, and includes VCATCH events (see System Control for descriptions of the events) if those events are enabled in the Debug Exception and Monitor Control Register (see Halting Debug Configuration and Status).

If not interpreted as a Hard Fault, the debug event is ignored.

This register is part of the Arm Cortex-M33 processor’s SCB register block.

For this peripheral’s registers, see Debug Control Block Registers.