### SENSOR_FIFO_CFG

Bit Field | Read/Write | Field Name | Description
--- | --- | --- | ---
12:8 | R | FIFO_LEVEL | Number of samples stored in FIFO
6 | RW | FIFO_RX_INT_EN | Enable / disable the interrupt when FIFO is full
5 | RW | FIFO_RX_DMA_EN | Enable / disable the DMA trigger when FIFIO is full
4 | RW | FIFO_STORE_EN | Enable the storage of sample on the FIFO
3:0 | RW | FIFO_SIZE | Number of samples stored before waking up the core

Bit Field | Field Name | Value Symbol | Value Description | Hex Value
--- | --- | --- | --- | ---
12:8 | FIFO_LEVEL | SENSOR_FIFO_EMPTY | FIFO data level is 0 | 0x0*
|  | SENSOR_FIFO_FULL | FIFO data level is 16 | 0x10
6 | FIFO_RX_INT_EN | FIFO_RX_INT_DISABLED | No RX interrupt | 0x0*
|  | FIFO_RX_INT_ENABLED | RX interrupt when FIFO is full | 0x1
5 | FIFO_RX_DMA_EN | FIFO_RX_DMA_DISABLED | No RX DMA triggered | 0x0*
|  | FIFO_RX_DMA_ENABLED | RX DMA triggered when FIFO is full | 0x1
4 | FIFO_STORE_EN | SENSOR_FIFO_STORE_DISABLED | Samples are not stored in the FIFO | 0x0
|  | SENSOR_FIFO_STORE_ENABLED | Samples are stored in the FIFO | 0x1*
3:0 | FIFO_SIZE | SENSOR_FIFO_SIZE1 | FIFO size 1; core wakes up after first sample arrives | 0x0*
|  | SENSOR_FIFO_SIZE2 | FIFO size 2 | 0x1
|  | SENSOR_FIFO_SIZE3 | FIFO size 3 | 0x2
|  | SENSOR_FIFO_SIZE4 | FIFO size 4 | 0x3
|  | SENSOR_FIFO_SIZE5 | FIFO size 5 | 0x4
|  | SENSOR_FIFO_SIZE6 | FIFO size 6 | 0x5
|  | SENSOR_FIFO_SIZE7 | FIFO size 7 | 0x6
|  | SENSOR_FIFO_SIZE8 | FIFO size 8 | 0x7
|  | SENSOR_FIFO_SIZE9 | FIFO size 9 | 0x8
|  | SENSOR_FIFO_SIZE10 | FIFO size 10 | 0x9
|  | SENSOR_FIFO_SIZE11 | FIFO size 11 | 0xA
|  | SENSOR_FIFO_SIZE12 | FIFO size 12 | 0xB
|  | SENSOR_FIFO_SIZE13 | FIFO size 13 | 0xC
|  | SENSOR_FIFO_SIZE14 | FIFO size 14 | 0xD
|  | SENSOR_FIFO_SIZE15 | FIFO size 15 | 0xE
|  | SENSOR_FIFO_SIZE16 | FIFO size 16 | 0xF