# LIN

The RSL15 system includes a local interconnect network (LIN) interface that allows the system to communicate with other devices via a LIN bus, which is typically used in an automobile's automotive system. The LIN module operates as a responder node on the bus, and supports version 2.2 of the LIN specification. The LIN port is an asynchronous 2-wire interface.

The LIN bus itself is a two wire interface, with one wire consisting of the LIN bus, and the other wire connected to ground. The LIN bus is a 12 V bus, and therefore cannot be interfaced directly to the RSL15 system. Instead, the RSL15's LIN interface must be connected to a LIN transceiver that converts the signals transmitted by the RSL15 system to a higher voltage that can be used on the LIN bus..

The LIN interface is multiplexed onto the GPIO pads, which can be configured as the input and output signals that the LIN interface utilizes, with the necessary physical pad configuration. For more information about configuring the multiplexed GPIO functionality, see General Purpose Input/Output.

The LIN interface itself only has one signal, the RX signal. This must be configured when one wishes to use the LIN interface. The TX signal can be implemented using a UART (see Universal Asynchronous Receiver-Transmitter (UART) Interfaces). The baud rate of the LIN bus is automatically retrieved from the LIN frame received. RSL15‘s LIN module supports a baud-rate of 1000-20000 b/s.

Data transfers using the LIN interface can be controlled directly by the processor, or indirectly using the DMA. The DMA can be triggered on LIN data reads via the DMA_CTRL register, using that register’s DMA_CTRL_TRIGGER_SOURCE bitfield.

## LIN Responder Mode

The LIN module that handles responder mode operations and the receiving of data from the LIN bus is controlled by a finite state machine (FSM). The FSM is started by enabling the interface via the LIN_CTRL_ENABLE bit in the LIN_CTRL register, and the LIN_CFG_INIT bit in the LIN_CFG register. Once these two bits have been set, the device must wait for 400 clock cycles for the FSM to initialize itself. When these 400 cycles are over, the interface prepares to start receiving data by entering a WAIT_BREAK_SYNC state. In this state, the module waits for a valid break and sync pattern from the LIN bus. Once this pattern is received, the module interprets the next data as the protected identifier (PID).

Upon reception of the PID, a LIN interrupt is fired and the LIN_CTRL_RHC bit in the LIN_CTRL register is set. In the LIN interrupt, the firmware is responsible for interpreting the PID and preparing the LIN module appropriately. Each unique PID has a different interpretation based on the design of the system. Each PID usually signifies if the current LIN frame is a read or write packet, as well as the length of the packet. Some PIDs include specially reserved values; these can be found by reviewing the LIN specification.

NOTE: When the LIN_CTRL register is read, it resets the value of the status bits.

Configuring the LIN module after interpreting the PID is a straightforward process. In both read and write frames, the length of the message is set by writing to the corresponding register. For writes, the frame length in bytes is written to the LIN_DLB_DLBT field of the LIN_DLB register. For reads, the frame length in bytes is written to the LIN_DLBR_DLBR field in the LIN_DLBR register. If writing data, the data to be written must then be written to the LIN_DATA bank of registers, starting at LIN_DATA0. The LIN_DATA_WORD* registers can also be used to provide a method for writing word sized data. Once the LIN_DATA* registers are written to, the LIN module handles either clocking out the LIN data on the TXD pin (via UART), or clocking the LIN data in on the RXD pin.

If the frame is a receive frame, another interrupt fires when the number of bytes set in the LIN_DLBR register are read. At this point, the LIN_CTRL_RXF bit in the LIN_CTRL register is set, and received data can be read from the LIN_DATA* registers. The LIN frame is now complete.

## Lin Commander Mode

The LIN commander node is responsible for starting and constructing the LIN frame. The LIN bus is pulled-up by default; therefore, a LIN frame consists of a break that includes 14 bits of low data. This BREAK sequence is followed by an alternating pattern of high and low levels, lasting eight bits (0x55). This is the SYNC sequence. These two sequences form the break-sync sequence, which indicates the start of a LIN frame. The LIN module looks for this pattern so it can start reception of the LIN frame. After the break, the commander device is responsible for sending the next byte, which contains the parity bits and PID, via UART. For information on how to calculate the parity bits, consult the LIN specification.

Since all the data that the LIN transceiver receives on its TXD pin is reflected back onto the RXD pin, the commander node starting the transmitted frame receives the same break sync sequence back, which triggers the LIN interrupt. At this point, the commander device responds to the interrupt in the same manner that responder mode does.

For registers, see LIN Registers.