# Direct Memory Access (DMA) Controller

## Block Overview

The direct memory access controller (DMA) module allows background transfers between components (referred to in this section as peripherals) on the peripheral bus, and memories, without any processor intervention. This allows the processors to be used for other computational needs while enabling high speed sustained transfers to and from the peripherals/memories.

The DMA has 4 independent configurable channels. Each channel can be configured for one of four modes:

| • | Data transferred from peripheral-to-memory (PM)

| • | Data transferred from memory-to-peripheral (MP)

| • | Data transferred between peripherals (PP)

| • | Data transferred between memory locations (MM)

The "DMA Overview" figure shows an overview of the module.

Figure: DMA Overview

There is a separate interrupt line available to the Arm Cortex-M33 core for each of the DMA channels. Each DMA channel can be configured to assert its interrupt line for several independent conditions, such as when a transfer, or a specified portion of it, is complete.

## Functional Description

### DMA to Peripherals Interface

The DMA supports several types of data transfers between the memories of the Arm Cortex-M33 processor and the interfaces and peripherals connected to the peripheral bus, including:

| • | Memory-to-Memory transfers

| • | Memory-to-Peripheral transfers

| • | Peripheral-to-Memory transfers

| • | Peripheral-to-Peripheral transfers

Each peripheral that supports DMA transfers is connected to the DMA controller through one or more DMA request signals. In most cases, a peripheral must be configured explicitly to operate in DMA mode to enable requests as required. The DMA supports 16 request lines from various peripherals included in RSL15, and is connected independently to each channel.

The interfaces and peripherals that are mapped onto the peripheral bus, and that are valid data sources and destinations for DMA data transfers, are listed in the "DMA Request Lines and their Associated Peripherals" table along with their associated request lines. DMA trigger lines and sources are shown in the "DMA Trigger Lines and Sources" table. For sources or destinations that do not need to wait for data (typically memories), no request timing is required so the transfer uses an always on (DMA_SRC_ALWAYS_ON, DMA_DEST_ALWAYS_ON) configuration. To select the desired source and destination, set the DMA_CFG0_SRC_SELECT and DMA_CFG0_DEST_SELECT bit-fields from the DMA_CFG0 register.

Table: DMA Request Lines and their Associated Peripherals

DMA Request Line | Peripheral | Source | Destination
0 | Always_on | DMA_SRC_ALWAYS_ON | DMA_DEST_ALWAYS_ON
1 | SPI0 | DMA_SRC_SPI0 | DMA_DEST_SPI0
2 | SPI1 | DMA_SRC_SPI1 | DMA_DEST_SPI1
3 | I2C0 | DMA_SRC_I2C0 | DMA_DEST_I2C0
4 | I2C1 | DMA_SRC_I2C1 | DMA_DEST_I2C1
5 | UART0 | DMA_SRC_UART0 | DMA_DEST_UART0
6 | PCM0 | DMA_SRC_PCM0 | DMA_DEST_PCM0
7 | TOF | DMA_SRC_TOF | DMA_DEST_TOF
8 | RF_IQ_READY | DMA_SRC_RF_IQ_READY | DMA_DEST_REQ_8
9 | R_ Phase_ ADC | DMA_SRC_RF_PHASE_ADC_READY | DMA_DEST_REQ_9
10 |  | Reserved |
11 |  | Reserved |
12 |  | Reserved |
13 |  | Reserved |
14 |  | Reserved |
15 |  | Reserved |

Table: DMA Trigger Lines and Sources
DMA Trigger Line | Source
--- | ---
0 | DMA Channel 0 completed
1 | DMA Channel 1 completed
2 | DMA Channel 2 completed
3 | DMA Channel 3 completed
4 | Sensor interface FIFO full
5 | LIN interface RX completed
6 | SAR interface RX completed
7 | Timer 0 interrupt
8 | Timer 1 interrupt
9 | Timer 2 interrupt
10 | Timer 3 interrupt
11 | Reserved
12 | Reserved
13 | Reserved
14 | Reserved
15 | Reserved

Each source interface or peripheral, when configured for DMA operation, asserts its DMA request signal when data can be read from the source. This signal is cleared automatically when a data value is read from the source using the peripheral bus.

CAUTION: When the DMA interface is used to control transfers that use an interface or peripheral, any access to that interface or peripheral's data registers using the peripheral bus clears the DMA request signals. If a DMA request signal is cleared due to a processor access, the underlying DMA transfer becomes corrupted.

NOTE: To ease understanding, throughout the remainder of this section all interfaces and peripherals used in DMA transfers are called peripherals due to their memory-mapping onto the peripheral bus.

### Configuration and Status

The "DMA Module Specification" table describes DMA supported configurations and specifications:

Table: DMA Module Specification

Item | Specification
Number of DMA Channels | 4
Priority Levels | 4
Maximum Transfer Length | 65536
Counter Interrupt Trigger Range | 1 – 65535
Configurable Modes | Increment or Circular
Types of Transfers | Memory to Peripheral (MP) Peripheral to Memory (PM) Memory to Memory (MM) Peripheral to Peripheral (PP)
Interrupt Lines | 8 (one per channel)
Interrupt Source per Channel | 3: Transfer length counter, Complete, Word counter
Word Sizes | 4-bit, 8-bit, 16-bit, and 32-bit

Each DMA channel can be configured independently through its associated memory mapped registers. Each DMA channel has one bit field, the DMA*_CTRL_MODE field of the DMA_CTRL register, which is used to enable one of the seven different modes in which the channel can be active (see the "DMA Channel Modes of Operation" table, below). The DMA channel can be deactivated at any time by setting the DMA_CTRL_MODE_ENABLE bit to DMA_DISABLE. If the DMA channel is in the midst of an operation when it is disabled, the current read or write transaction is completed. All pending bus requests are subsequently aborted when the channel is disabled.

Table: DMA Channel Modes of Operation

MODE_ENABLE Bit Value | Constant | Remarks
0 | DMA_DISABLE | Disable the DMA channel (channel waits on current READ or WRITE access to finish before the active bit is cleared)
1 | DMA_ENABLE | Immediately enable the DMA channel, and when the transfer is completed, disable the DMA channel
2 | DMA_ENABLE_WRAP | Immediately enable the DMA channel, and when the transfer is completed, wrap addresses and disable the DMA channel
3 | DMA_ENABLE_WRAP_RESTART | Immediately enable the DMA channel, and when the transfer is completed, wrap addresses and restart the transfer
4 | DMA_TRIGGER | When the source trigger occurs, enable the DMA channel; when the transfer is completed, disable the DMA channel
5 | DMA_TRIGGER_WRAP | When the source trigger occurs, enable the DMA channel; when the transfer is completed, wrap addresses and disable the DMA channel
6 | DMA_TRIGGER_WRAP_RESTART | When the source trigger occurs, enable the DMA channel; when the transfer is completed, wrap addresses and restart the DMA channel
7 | DMA_TRIGGER_WRAP_TRIGGER_RESTART | When the source trigger occurs, enable the DMA channel; when the transfer is completed, wrap addresses, and upon next trigger event, restart the DMA channel

The DMA interface has eight modes of operation. These modes can be roughly divided into two groups: the manual modes (DMA_ENABLE, DMA_ENABLE_WRAP, and DMA_ENABLE_WRAP_RESTART) and the trigger modes (DMA_TRIGGER, DMA_TRIGGER_WRAP, DMA_TRIGGER_WRAP_RESTART, and DMA_TRIGGER_WRAP_TRIGGER_RESTART). The two mode groups differ in how a transfer is started in each group. In a manual (non-trigger) mode, the transfer start is controlled by the user application. One such application would be a memory-to-memory buffer copy operation or a memory-to-peripheral transfer to a communication interface or a peripheral. In a trigger mode, a transfer is started by a trigger event configured through the DEST_SELECT and SRC_SELECT bits in the DMA[0:3]_CFG0 register. Typical applications of this mode are peripheral-to-memory transfers.

The DMA_ENABLE and DMA_TRIGGER modes are one-shot modes that are used when the user application controls the start and address of the DMA channel. The application has to set up the addresses after each transfer.

The DMA_ENABLE_WRAP and DMA_TRIGGER_WRAP are also one-shot modes. In these modes, the user application needs to set up the addresses for the first transfer. After completing a transfer, the addresses are wrapped by the hardware and left ready for the next transfer. This is useful for implementing circular buffers.

In the DMA_ENABLE_WRAP_RESTART and DMA_TRIGGER_WRAP_RESTART modes, the DMA interface is run in a continuous mode. It keeps running until manually stopped by the user application. The addresses are automatically wrapped by the hardware at the end of each transfer.

The DMA_TRIGGER_WRAP_TRIGGER_RESTART mode differs from the two previous modes in that the interface is not continuously run. Each transfer is automatically started by a trigger event without user intervention, and the addresses are wrapped by the hardware.

Trigger modes are further explained in Direct Memory Access (DMA) Controller.

Other DMA channel configurations include:

Source and Destination Address Configuration

The DMA_SRC_ADDR registers define the base address of the source data for a DMA channel. The DMA_DEST_ADDR registers define the base address of the destination data for a DMA channel. The DMA supports byte addressing for source and destination addresses. Smaller word sizes are supported indirectly by selecting the source and destination word sizes, and through packing and unpacking. The DMA calculates the next source address and the next destination address by using the current counter value.

These addresses need to be word-aligned, a requirement for the 32-bit accesses that this block performs. If a non-aligned address is configured, the DMA ignores the two LSBs, making the transfer word-aligned.

Each DMA channel can be configured for two address modes: linear and circular. These address modes are selected while defining the mode of operation in the DMA control registers.

• In linear address mode, the DMA operation occurs and then the DMA channel is automatically disabled once the transfer is complete. The source and destination addresses are not reset to predefined addresses.

• In wrap restart mode (circular address mode), the DMA operation occurs and then the DMA channel configuration is reset to the initial configuration once the transfer is completed. This configuration includes current source address, current destination address, and length of transfer. The DMA channel remains enabled, continuing to run until explicitly stopped by the firmware when it sets the appropriate enabling bit to a disabled status.

• In wrap linear mode, the addresses are wrapped at the end before the DMA channel is disabled. This sets up the memory block for the next transfer.

• Each DMA channel has independent increment and decrement controls: between -8 and +7, with a step size of 1, for both source and destination addresses. The required step size can be configured using the DMA_CFG0_SRC_ADDR_STEP and DMA_CFG0_DEST_ADDR_STEP bit fields in the DMA_CFG0 registers, for the source and destination addresses respectively. When the addressing step size is set to DMA_DEST_ADDR_STATIC, the address is neither incremented nor decremented after each word is transferred, i.e., it remains static. The address step size is applied to the address after each word is transferred. For example, in Memory-to-Peripheral operations, typically the source has the increment enabled, while the destination has the increment disabled.

NOTE: The source and destination address registers are not modified during a transfer; the increment setting only affects the calculation of the next address. When disabled, the next address is always equal to the base address.

Source and Destination Data

The source and destination data can be configured to be interpreted as being packed into a variety of different word sizes and endian ordering. For more information, see Packing and Unpacking.

Transfer Length and Counter Interrupt Configuration

The DMA channels support variable transfer lengths up to 216 packed words (32 bits per word). The length of a transfer can be set using the DMA_CFG1_TRANSFER_LENGTH bit field in the DMA_CFG1 registers. When the DMA channel completes transferring this length of data to the destination, the DMA_STATUS_COMPLETE_INT flag is set, and an interrupt is generated if the DMA_CFG0_COMPLETE_INT_ENABLE bit is set in the DMA_CFG0 registers.

The application can set a re-configurable trigger level for 1 to 216 words in the DMA_CFG1_INT_TRANSFER_LENGTH bit field of the DMA_CFG1 register for each DMA channel; set the field to 0 to disable it. When a channel’s current transfer counter reaches the trigger level, an interrupt is generated if the counter interrupt is enabled, and all the data inside the source buffer register DMA_SRC_BUFFER is written to the destination.

Interrupt Configuration.

The interrupts used to coordinate with, and control, a DMA transfer can be defined using the DMA_CFG*_COMPLETE_INT_ENABLE and DMA_CFG*_CNT_INT_ENABLE bits from the DMA channel's DMA_CFG* registers. For more information, see DMA Interrupt Configuration.

Transfer Priority.

The relative priority of this DMA channel's transfer. For more information, see DMA Channel Arbiter.

IMPORTANT: The DMA channel uses counters to calculate the next source address and next destination address. The base source address, base destination address, and starting length remain unchanged. Only the counter value is modified during a transfer. This allows the DMA channel configuration to be reused (either explicitly through firmware or in circular mode) without rewriting the configuration register for multiple transfers.

The DMA channels each contain a status register (DMA_STATUS), indicating the completion status of the transfer (active, idle or complete), and the channel's interrupt status. The firmware can use this to quickly assess the status of a DMA channel.

IMPORTANT: When a DMA channel is enabled, the DMA_STATUS_ACTIVE bit in the DMA_STATUS register stays low for one cycle. This can cause a problem when polling the DMA_STATUS_ACTIVE bit directly after enabling the channel, as the DMA status is incorrect for the first cycle (this only affects optimized C or assembly code). Make sure there is at least one operation (such as a NOP) between enabling the DMA channel and polling the DMS_STATUS_ACTIVE bit.

The DMA channel can be paused by disabling it. If the current transaction is a read, the interface fills up the source buffer and is ready for a write transfer. The channel configuration is not cleared unless the DMA_CTRL_BUFFER_CLEAR and DMA_CTRL_CNTS_CLEAR bits in the DMA_CTRL register are set.

In some cases, you might wish to re-assign a DMA channel that is already in use. In this case, you probably need to save the current state of the DMA and restore and restart it later. To do so, perform the following steps:

For saving the state of the DMA:

1. Disable the selected DMA channel by issuing DMA_DISABLE (clearing the DMA_CTRL_MODE_ENABLE bit-field) to the corresponding DMA_CTRL register, without affecting any other settings in that register.
2. Wait until the value of the DMA_STATUS_ACTIVE bit in the DMA_STATUS register becomes zero.
3. Save state of the DMA_CTRL, DMA_CFG0, DMA_CFG1, DMA_STATUS, DMA_SRC_ADDR, DMA_DEST_ADDR, and DMA_SRC_BUFFER registers.

For restoring and restarting the DMA:

1. Write all of the above saved data back to the desired DMA channel’s registers.
2. When restoring DMA_STATUS, ensure that the saved value is logical OR’ed with DMA_SRC_BUFFER_FILL_LVL_WR to enable writing the buffer fill level.
3. Once this is done, write the appropriate DMA_ENABLE command to the DMA_CTRL_MODE_ENABLE bit-field of the DMA_CTRL register.

### DMA Interrupt Configuration

The DMA provides separate interrupts to the core for each channel independently. Each DMA channel can be configured using its DMA_CFG0 register to assert an interrupt for several independent conditions:

A transfer has reached the counter interrupt value

Set the DMA_CFG1_INT_TRANSFER_LENGTH bit field in the channel's DMA_CFG1 register, as defined by the DMA_CFG1_TRANSFER_LENGTH bit field in the channel's DMA_CFG1 register, to a non zero value to configure a trigger level, and set the DMA_CFG0_COUNTER_INT_ENABLE bit to enable it. If the counter is set to n, the transfer reaches the counter interrupt value when it writes the nth memory word to the DMA channel's destination. This counter can be cleared using the DMA_CTRL_BUFFER_CLEAR and DMA_CTRL_CNTS_CLEAR bits in the DMA_CTRL register. This interrupt can be used to allow the firmware to operate on partial blocks of data as they are available.

A transfer is complete

Set the DMA_CFG0_COMPLETE_INT_ENABLE bit to enable this interrupt. A transfer is considered complete when the last word is written to the DMA channel's destination. For wrap restart transfers (circular transfers), a complete interrupt is generated each time the circular transfer is completed.

The interrupts for DMA are configurable on a per-channel basis using the DMA_CFG0 registers. A user application can read sticky bits DMA_STATUS_CNT_INT and DMA_STATUS_COMPLETE_INT in the channel status registers (DMA_STATUS) to know which interrupts have been triggered. Consequently, the user application can clear sticky status bits of the interrupts by writing to the DMA_STATUS_COMPLETE_INT_CLEAR or DMA_STATUS_COMPLETE_INT_CLEAR bit fields.

NOTE: If a status bit for a particular event is not cleared, all subsequent interrupts for that same event are masked.

### Circular Mode

By enabling DMA_CFG*_SRC_ADDR_LSB_TOGGLE, a DMA transfer can have its source address effective LSB toggled after each read, resulting in a circular buffer of 2 words. DMA_CFG0*_SRC_ADDR_STEP_SIZE must be set to zero in this case. For a source word size of 4 or 8 bits, address bit 0 is toggled; for a source word size of 16 bits, address bit 1 is toggled; and for a source word size of 32 bits, address bit 2 is toggled.

By enabling DMA_CFG*_DEST_ADDR_LSB_TOGGLE, a DMA transfer can have its destination address's effective LSB toggled after each write, resulting in a circular buffer of 2 words. DMA_CFG0*_DEST_ADDR_STEP_SIZE must be set to zero in this case. For a destination word size of 4 or 8 bits, address bit 0 is toggled; for a destination word size of 16 bits, address bit 1 is toggled; and for a destination word size of 32 bits, address 2 is toggled.

### Word Size

Each DMA channel can have different word sizes set for both the source and the destination. The word sizes for the source and destination data can be configured as 4-bit, 8-bit, 16-bit, or 32-bit, using the DMA_CFG0_SRC_DEST_WORD_SIZE bit field from the DMA_CFG0* register. Smaller word sizes can be used to optimize memory utilization when retrieving or storing data. Both 4-bit and 8-bit words are byte addressable, 16-bit words are half word addressable, and 32-bit words are word addressable in memory.

The "Organization of a 32-Bit memory instance" figure shows the organization of a 32-bit memory instance. From the DMA perspective, it can be comprised of the following:

| • | One 32-bit word (word 0), or

| • | Two 16-bit words (word 0, word 1), or

| • | Four 8-bit words (word 0, word 1, word 2, word 3), or

| • | Eight 4-bit words (word 0, word 1, word 2, word 3, word 4, word 5, word 6, word 7)

Figure: Organization of a 32-Bit memory instance

Read bus operations are always based on 32-bit words. However, the DMA can utilize only a portion of the data if the selected word sizes are smaller. Write bus operations can be 8-bit, 16-bit, or 32-bit words, as long as the memory system that is addressed supports this. The counter in the DMA channel always operates on the configured source word size. If the transfer type is memory-peripheral, the length sets the number of destination words transferred; otherwise it sets the number of source words transferred.The next address for reading or writing can be determined from the configured word size, the current counter, and the base address. This might result in an actual read or write, or use of the temporary register with the DMA.

### Packing and Unpacking

When the source or destination word sizes are different, the DMA performs packing and/or unpacking (shown in the "DMA Packing and Unpacking" figure) as required. When packing data, the DMA channel reads and packs input data into an internal buffer that is accessible through the DMA_SRC_BUFFER registers. When the DMA channel is unpacking data, it uses the same buffer as the source of packed data. This access is provided to the application so that it can recover from a partial data transfer. In the case of a partial transfer from a serial interface, for example, the data is available in the internal buffer.

Packing and unpacking are performed automatically, depending on the word size configuration, the byte address access, and the DMA operation mode. Packing and unpacking can be used for all types of DMA transfers, to minimize bus utilization and maximize memory use efficiency. For example, when writing four bytes to an 8-bit destination register, only one 32-bit read is required from the source memory instance. In this case, the memory instance word size is configured as 32-bit, and the peripheral word size is configured as 8-bit. When both source and destination are configured for the native word size (32-bit), no special processing is necessary (direct mode).

The data is always right aligned and can be byte addressable. When the destination word size is less than 32 bits and the destination address is not byte addressed, the data is stored in the lower portion of the 32-bit word. The upper bits are always written as zero (padded mode). When the source word size is less than 32 bits, the data is read from the lower portion of the 32-bit word. The upper bits are ignored. In addition to packing/unpacking, the DMA supports both big and little endian transfers.

NOTE: Transfers that cannot be evenly packed into the destination word size (i.e., transfers that include an incomplete final word) are only supported for little endian transfers.

If byte ordering is enabled, the DMA can also order the bytes when the source word size and destination word size are the same. In the case of a word size of 8 bits for both source and destination, the nibble is ordered instead. No ordering occurs for word sizes of 4 bits. This is shown in the two examples that follow.

| • | Example 1 (see also the "DMA Transfer with Src Word Size < Dest Word Size (Example 1)" table, below):

| ◦ | Transfer Type: Peripheral to Memory

| ◦ | Source Word Size: 8 bits (Peripheral, for instance SPI output)

| ◦ | Destination Word Size: 32 bits (Data Memory)

| ◦ | Transfer Length: 5

| ◦ | Byte Ordering: Little Endian

Table: DMA Transfer with Src Word Size < Dest Word Size (Example 1)

SOURCE | DESTINATION (Data Memory)
WordInput_8_0 |
WordInput_8_1 |
WordInput_8_2 |
WordInput_8_3 | WordOutput_32_0 = {WI8_3, WI8_2, WI8_1, WI8_0}
WordInput_8_4 | WordOutput_32_1 = {{0x00, 0x00, 0x00, WI8_4}

| • | Example 2 (see also the "DMA Transfer with Src Word Size < Dest Word Size (Example 2)" table, below):

| ◦ | Transfer Type: Peripheral to Memory

| ◦ | Source Word Size: 8 bits (Peripheral, for instance SPI output)

| ◦ | Destination Word Size: 16 bits (Data Memory)

| ◦ | Transfer Length: 5

| ◦ | Byte Ordering: Big Endian

Table: DMA Transfer with Src Word Size < Dest Word Size (Example 2)

SOURCE | DESTINATION (Data Memory)
WordInput_8_0 |
WordInput_8_1 | WordOutput_32_0 = {0x00, 0x00, WI8_0, WI8_1}
WordInput_8_2 |
WordInput_8_3 | WordOutput_32_1 = {0x00, 0x00, WI8_2, WI8_3}
WordInput_8_4 | WordOutput_32_2 = {0x00, 0x00, WI8_4, 0x00}

When packing data, the DMA channel reads and packs input data into an internal buffer that is accessible through the DMA_SRC_BUFFER registers. When the DMA channel is unpacking data, it uses the same buffer as the source of packed data. The "DMA Packing and Unpacking" figure shows the DMA packing and unpacking format.

Figure: DMA Packing and Unpacking

DMA channels can be triggered to start without firmware intervention, based on another DMA channel completing or a specified system interrupt occurring. This can be used to off-load interrupts and data transfer tasks from the Arm Cortex-M33 processor.

The start of the DMA transfer is defined by the triggering enable modes. For example, one DMA channel can send data to the CRC module, while a second DMA channel can pull data from the CRC module without the Arm Cortex-M33 core's intervention. In any triggering mode, the DMA channel waits until a configured triggering event occurs. This triggering event is defined by the DMA_CTRL_TRIGGER_SOURCE field in the DMA_CTRL registers.

Each DMA channel needs to be configured independently (i.e., different transfer length, word sizes, increment steps, source, destination, etc.).

IMPORTANT: A DMA channel must not be configured to be triggered by itself, or else the channel remains in pending state (DMA_STATUS_DMA_STATUS_ACTIVE).

NOTE: If two or more DMA channels are linked to the same trigger source, they run in parallel and start new DMA threads. Any conflict associated with cross-selecting DMA channels needs to be controlled by the firmware.

The destination counter value indicates the number of transfers sent to the destination address during each DMA transfer. Upon completion, the complete interrupt of the corresponding DMA channel is triggered if enabled.

At the end of the DMA transfer, the selected triggering mode can define how the channel behaves when the transfer length is reached:

| • | If DMA_TRIGGER has been selected, the channel is disabled automatically, with no address wrapping.

| • | If DMA_TRIGGER_WRAP has been selected, the addresses are wrapped to the configured base addresses and the channel is disabled.

| • | If DMA_TRIGGER_WRAP_RESTART has been selected, the addresses are wrapped to the configured base addresses, and the channel restarts with another DMA transfer in a circular addressing mode with the same channel configuration. In this mode, the loop is broken when the DMA channel is disabled with the firmware's intervention.

| • | If DMA_TRIGGER_WRAP_TRIGGER_RESTART has been selected, the addresses are wrapped to the configured base addresses, the transfer counter is reset, and the DMA channel becomes pending, waits to be triggered again, and restarts with another DMA transfer.

NOTE: Source or destination addresses (depending on SRC_DEST_TRANS_LENGTH_SEL) can also be wrapped on every interrupt transfer length counter, as configured using the DMA_CTRL_INT_CNT_ADDR_WRAP_ENABLE bit from the DMA_CTRL register.

### DMA Operation

The DMA controller works as follows:

| 1. | The DMA channel is configured and enabled by the firmware.

| a. | The operation sequence varies slightly if the transfer length depends on the destination or source word count. This can be selected using the bit location DMA_CFG0_SRC_DEST_TRANS_LENGTH_SEL in the DMA_CFG0 register.

| b. | If bit DMA_CFG0_SRC_DEST_TRANS_LENGTH_SEL is set to DEST_TRANS_LENGTH_SEL, the transfer length depends on the destination transfer count. When SRC_TRANS_LENGTH_SEL is set, the transfer length depends on the source word count.

| 2. | The operation sequence is as follows when the transfer length depends on the destination word count:

| a. | The DMA channel reads from the source until its source buffer is filled with enough bits to write to its destination, in accordance with its word size.

| i. | If the DMA source request line is configured to be connected to a peripheral with DMA access, the channel reads from the source address when a request is issued by the peripheral.

| ii. | If DMA access is not available, or if the source is a memory location, then DMA_SRC_ALWAYS_ON can be selected, and the DMA channel reads immediately.

| iii. | The DMA channel reads from the source until its source buffer is filled with enough bits to write to its destination, in accordance with its word size.

| b. | As the source buffer is read by DMA, the DMA_STATUS_SRC_BUFFER_FILL_LVL bit-field in the DMA_STATUS register is updated to reflect the new source buffer status. The DMA channel writes to its destination, as long as the source buffer contains enough bits for the writing task and the destination word counter is less than the configured transfer length.

| i. | If the DMA destination request line is configured to be connected to a peripheral with DMA access, the channel writes to the destination when this request is made by the peripheral.

| ii. | If DMA access is not available, or if the source is a memory location, then DMA_DEST_ALWAYS_ON is selected as the destination and the DMA channel writes immediately.

| iii. | When data is read by the DMA from the source or destination address, the data is copied into the DMA_SRC_BUFFER register. The data in this register is shifted to the right in accordance with the destination word size, and zeroes are shifted in. The DMA_STATUS_SRC_BUFFER_FILL_LVL field in the DMA0_STATUS register is updated to reflect the new source buffer status.

| iv. | The DMA continues to transfer data from source to destination, until the destination transfer length (configured through the DMA_CFG1_TRANSFER_LENGTH field in the DMA_CFG1 registers) is reached. The DMA increments a destination word counter which can be read by the DMA_CNTS_TRANSFER_WORD_CNT field in the DMA_CNTS registers.

| c. | An interrupt can be generated for a transfer word count by writing to the DMA_CFG1_INT_TRANSFER_LENGTH field in the DMA_CFG1 registers. This transfer word count is incremented with the destination word counter of the DMA. If a non zero value for the interrupt transfer word count is written in the register, and the interrupt transfer word count in the register value reaches the configured value, an interrupt triggers, the interrupt status bit is set, and the counter resets and begins to count again. The transfer word counter continues counting and generating interrupts in the same manner until the DMA operation is complete.

| d. | When the destination word count equals the transfer word count, the DMA channel triggers a completed interrupt (when it is enabled), its interrupt state bit is set, and the counter resets only in continuous modes.

| 3. | The operation is as follows when the transfer length depends on the source word count:

| a. | The source word counter is incremented until it reaches the transfer word count. The counter resets only in continuous modes.

| b. | When the destination word count equals the transfer word count, the DMA channel triggers a completed interrupt when it is enabled and its interrupt state bit is set. However, in this mode, if the DMA transfer is not completed, the channel restarts its operation.

### DMA Channel Arbiter

Only one transfer using the DMA channels can be actively serviced at a time. The DMA contains a channel arbiter, which is responsible for determining which DMA channel to activate. Each DMA channel is assigned a channel priority in the range of 0 - 3, using the DMA_CFG0_CHANNEL_PRIORITY bit-field from the DMA_CFG0 registers. This channel priority is used by the arbiter to determine which DMA channel to service when multiple requests are pending.

Each DMA channel receives respective requests from peripherals connected to the DMA request lines. Once the DMA channel is ready to begin an operation, it indicates to the arbiter that it is ready by making a request. The DMA arbiter selects between multiple ready DMA channels based on configured channel priority.

The following situations describe scenarios when multiple requests might be pending:

| • | A DMA request is asserted by two or more peripherals (or a single peripheral serving two DMA channels) during the same clock cycle.

| • | One or more DMA requests come in during the processing of another DMA request.

| • | A DMA channel is enabled with multiple requests already pending.

When choosing which DMA channel to activate, the DMA arbiter applies the channel's priority settings as follows:

| • | When multiple channels are ready, the channel with the highest channel priority setting is activated.

| • | If more than one channel is ready to be activated and they have the same priority setting, the lowest numbered channel is activated.

When a single channel is ready, the arbiter grants access and the channel begins to service that request immediately.

IMPORTANT: A lower priority DMA channel might never be served if a higher priority DMA channel is generating requests too fast. This type of situation must be avoided by application design.

For registers, see DMA Registers.