# I2C Interface

Address | Register Name | Register Write | Register Read | Default | Description
--- | --- | --- | --- | --- | ---
0x40000D00 | I2C0_CFG | (30) REPEATED_START_INT_ENABLE | (30) REPEATED_START_INT_ENABLE | 0x0 | Configure whether repeated start interrupts will be generated by the I2C interface for active transactions in slave mode
|  | (29) CONNECT_IN_STANDBY | (29) CONNECT_IN_STANDBY | 0x0 | Control if the I2C lines are connected when running on the standby clock
|  | (28) TX_DMA_ENABLE | (28) TX_DMA_ENABLE | 0x0 | Enable/disable the TX DMA request
|  | (27) RX_DMA_ENABLE | (27) RX_DMA_ENABLE | 0x0 | Enable/disable the RX DMA request
|  | (26) TX_INT_ENABLE | (26) TX_INT_ENABLE | 0x0 | Enable/disable the TX interrupt
|  | (25) RX_INT_ENABLE | (25) RX_INT_ENABLE | 0x0 | Enable/disable the RX interrupt
|  | (24) BUS_ERROR_INT_ENABLE | (24) BUS_ERROR_INT_ENABLE | 0x0 | Enable/disable the bus error interrupt
|  | (23) OVERRUN_INT_ENABLE | (23) OVERRUN_INT_ENABLE | 0x0 | Enable/disable the overrun interrupt
|  | (22) STOP_INT_ENABLE | (22) STOP_INT_ENABLE | 0x0 | Configure whether stop interrupts will be generated by the I2C interface
|  | (21) AUTO_ACK_ENABLE | (21) AUTO_ACK_ENABLE | 0x0 | Select whether acknowledgement is automatically generated or not
|  | (20:16) SLAVE_PRESCALE | (20:16) SLAVE_PRESCALE | 0x0 | Controls the number of SYSCLK wait cycles in case of clock streching (in slave mode) between the moment the data is put on the SDA line and the SCL line is released.
|  | (15:8) MASTER_PRESCALE | (15:8) MASTER_PRESCALE | 0x0 | Prescaler used to divide SYSCLK to the correct SCL frequency when operating in master mode. SCL is prescaled by (PRESCALE + 1) * 3.
|  | (7:1) SLAVE_ADDRESS | (7:1) SLAVE_ADDRESS | 0x10 | Set the I2C slave address for this device
|  | (0) SLAVE | (0) SLAVE | 0x0 | Select whether the I2C interface is enabled for slave mode or not
0x40000D04 | I2C0_CTRL | - | (9) LAST_DATA_STATUS | 0x0 | I2C last data status
|  | - | (8) ENABLE_STATUS | 0x0 | I2C enable status
|  | (6) LAST_DATA | - | N/A | Indicate that the current data is the last byte of a data transfer
|  | (5) STOP | - | N/A | Issue a stop condition on the I2C interface bus
|  | (4) NACK | - | N/A | Issue a not acknowledge on the I2C interface bus
|  | (3) ACK | - | N/A | Issue an acknowledge on the I2C interface bus
|  | (2) RESET | - | N/A | Reset the I2C interface
|  | (1) DISABLE | - | N/A | Disable the I2C interface
|  | (0) ENABLE | - | N/A | Enable the I2C interface
0x40000D08 | I2C0_ADDR_START | (7:1) ADDRESS | (7:1) ADDRESS | 0x0 | I2C address to use for the transaction
|  | (0) READ_WRITE | (0) READ_WRITE | 0x0 | Select whether a read or a write transaction is started
0x40000D0C | I2C0_STATUS | - | (26) STOP_OR_REPEATED_START_DETECTED | 0x0 | Indicate if STOP_DETECTED or REPEATED_START_DETECTED bit is set
|  | - | (25) REPEATED_START_DETECTED | 0x0 | Indicate if an I2C repeated start has been detected during an active transaction in slave mode
|  | - | (22) BUS_ERROR | 0x0 | Bus error status bit
|  | - | (21) BUSY | 0x0 | Indicate that the reception or transmission of the data is ongoing
|  | - | (20) START_PENDING | 0x0 | Master frame start pending status bit
|  | - | (19) MASTER_MODE | 0x0 | Master mode status bit
|  | - | (18) STOP_DETECTED | 0x0 | Indicate if an I2C stop bit has been detected
|  | - | (17) DATA_EVENT | 0x0 | Indicate that I2C interface either needs data to transmit or has received data
|  | - | (16) TX_REQ | 0x1 | Indicate that a TX data can be written
|  | - | (15) RX_REQ | 0x0 | Indicate that a RX data can be read
|  | - | (14) CLK_STRETCH | 0x0 | Clock stretching flag
|  | - | (13) LINE_FREE | 0x1 | Line free flag
|  | - | (12) ADDR_DATA | 0x0 | Address / Data byte
|  | - | (11) READ_WRITE | 0x0 | Read / Write frame
|  | - | (10) GEN_CALL | 0x0 | General call flag
|  | - | (9) ACK | 0x0 | Acknowledge status
|  | - | (8) OVERRUN | 0x0 | Indicate that an overrun has occurred when receiving data
|  | (4) TX_REQ_SET | - | N/A | Set TX_REQ status flag
|  | (3) REPEATED_START_DETECTED_CLEAR | - | N/A | Clear REPEATED_START_DETECTED status flag
|  | (2) STOP_DETECTED_CLEAR | - | N/A | Clear STOP_DETECTED status flag
|  | (1) BUS_ERROR_CLEAR | - | N/A | Clear BUS_ERROR status flag
|  | (0) OVERRUN_CLEAR | - | N/A | Clear OVERRUN status flag
0x40000D10 | I2C0_TX_DATA | (7:0) TX_DATA | (7:0) TX_DATA | 0x0 | Single byte buffer for data transmitted over the I2C interface
0x40000D14 | I2C0_RX_DATA | - | (7:0) RX_DATA | 0x0 | Single byte buffer for data received over the I2C interface
0x40000D18 | I2C0_RX_DATA_MIRROR |  |  |  |
0x40000DFC | I2C0_ID_NUM | - | (22) I2C_WATCHDOG | 0x0 | Implementation of the watchdog counter
|  | - | (21) I2C_DEBUG | 0x0 | Implementation of the debug interface
|  | - | (20) I2C_DMA | 0x0 | Implementation of the DMA interface
|  | - | (19:16) I2C_NUMBER | 0x0 | I2C instance number
|  | - | (15:8) I2C_MAJOR_REVISION | 0x1 | I2C Major Revision number
|  | - | (7:0) I2C_MINOR_REVISION | 0x0 | I2C Minor Revision number
0x40000E00 | I2C1_CFG | (30) REPEATED_START_INT_ENABLE | (30) REPEATED_START_INT_ENABLE | 0x0 | Configure whether repeated start interrupts will be generated by the I2C interface for active transactions in slave mode
|  | (29) CONNECT_IN_STANDBY | (29) CONNECT_IN_STANDBY | 0x0 | Control if the I2C lines are connected when running on the standby clock
|  | (28) TX_DMA_ENABLE | (28) TX_DMA_ENABLE | 0x0 | Enable/disable the TX DMA request
|  | (27) RX_DMA_ENABLE | (27) RX_DMA_ENABLE | 0x0 | Enable/disable the RX DMA request
|  | (26) TX_INT_ENABLE | (26) TX_INT_ENABLE | 0x0 | Enable/disable the TX interrupt
|  | (25) RX_INT_ENABLE | (25) RX_INT_ENABLE | 0x0 | Enable/disable the RX interrupt
|  | (24) BUS_ERROR_INT_ENABLE | (24) BUS_ERROR_INT_ENABLE | 0x0 | Enable/disable the bus error interrupt
|  | (23) OVERRUN_INT_ENABLE | (23) OVERRUN_INT_ENABLE | 0x0 | Enable/disable the overrun interrupt
|  | (22) STOP_INT_ENABLE | (22) STOP_INT_ENABLE | 0x0 | Configure whether stop interrupts will be generated by the I2C interface
|  | (21) AUTO_ACK_ENABLE | (21) AUTO_ACK_ENABLE | 0x0 | Select whether acknowledgement is automatically generated or not
|  | (20:16) SLAVE_PRESCALE | (20:16) SLAVE_PRESCALE | 0x0 | Controls the number of SYSCLK wait cycles in case of clock streching (in slave mode) between the moment the data is put on the SDA line and the SCL line is released.
|  | (15:8) MASTER_PRESCALE | (15:8) MASTER_PRESCALE | 0x0 | Prescaler used to divide SYSCLK to the correct SCL frequency when operating in master mode. SCL is prescaled by (PRESCALE + 1) * 3.
|  | (7:1) SLAVE_ADDRESS | (7:1) SLAVE_ADDRESS | 0x10 | Set the I2C slave address for this device
|  | (0) SLAVE | (0) SLAVE | 0x0 | Select whether the I2C interface is enabled for slave mode or not
0x40000E04 | I2C1_CTRL | - | (9) LAST_DATA_STATUS | 0x0 | I2C last data status
|  | - | (8) ENABLE_STATUS | 0x0 | I2C enable status
|  | (6) LAST_DATA | - | N/A | Indicate that the current data is the last byte of a data transfer
|  | (5) STOP | - | N/A | Issue a stop condition on the I2C interface bus
|  | (4) NACK | - | N/A | Issue a not acknowledge on the I2C interface bus
|  | (3) ACK | - | N/A | Issue an acknowledge on the I2C interface bus
|  | (2) RESET | - | N/A | Reset the I2C interface
|  | (1) DISABLE | - | N/A | Disable the I2C interface
|  | (0) ENABLE | - | N/A | Enable the I2C interface
0x40000E08 | I2C1_ADDR_START | (7:1) ADDRESS | (7:1) ADDRESS | 0x0 | I2C address to use for the transaction
|  | (0) READ_WRITE | (0) READ_WRITE | 0x0 | Select whether a read or a write transaction is started
0x40000E0C | I2C1_STATUS | - | (26) STOP_OR_REPEATED_START_DETECTED | 0x0 | Indicate if STOP_DETECTED or REPEATED_START_DETECTED bit is set
|  | - | (25) REPEATED_START_DETECTED | 0x0 | Indicate if an I2C repeated start has been detected during an active transaction in slave mode
|  | - | (22) BUS_ERROR | 0x0 | Bus error status bit
|  | - | (21) BUSY | 0x0 | Indicate that the reception or transmission of the data is ongoing
|  | - | (20) START_PENDING | 0x0 | Master frame start pending status bit
|  | - | (19) MASTER_MODE | 0x0 | Master mode status bit
|  | - | (18) STOP_DETECTED | 0x0 | Indicate if an I2C stop bit has been detected
|  | - | (17) DATA_EVENT | 0x0 | Indicate that I2C interface either needs data to transmit or has received data
|  | - | (16) TX_REQ | 0x1 | Indicate that a TX data can be written
|  | - | (15) RX_REQ | 0x0 | Indicate that a RX data can be read
|  | - | (14) CLK_STRETCH | 0x0 | Clock stretching flag
|  | - | (13) LINE_FREE | 0x1 | Line free flag
|  | - | (12) ADDR_DATA | 0x0 | Address / Data byte
|  | - | (11) READ_WRITE | 0x0 | Read / Write frame
|  | - | (10) GEN_CALL | 0x0 | General call flag
|  | - | (9) ACK | 0x0 | Acknowledge status
|  | - | (8) OVERRUN | 0x0 | Indicate that an overrun has occurred when receiving data
|  | (4) TX_REQ_SET | - | N/A | Set TX_REQ status flag
|  | (3) REPEATED_START_DETECTED_CLEAR | - | N/A | Clear REPEATED_START_DETECTED status flag
|  | (2) STOP_DETECTED_CLEAR | - | N/A | Clear STOP_DETECTED status flag
|  | (1) BUS_ERROR_CLEAR | - | N/A | Clear BUS_ERROR status flag
|  | (0) OVERRUN_CLEAR | - | N/A | Clear OVERRUN status flag
0x40000E10 | I2C1_TX_DATA | (7:0) TX_DATA | (7:0) TX_DATA | 0x0 | Single byte buffer for data transmitted over the I2C interface
0x40000E14 | I2C1_RX_DATA | - | (7:0) RX_DATA | 0x0 | Single byte buffer for data received over the I2C interface
0x40000E18 | I2C1_RX_DATA_MIRROR |  |  |  |
0x40000EFC | I2C1_ID_NUM | - | (22) I2C_WATCHDOG | 0x0 | Implementation of the watchdog counter
|  | - | (21) I2C_DEBUG | 0x0 | Implementation of the debug interface
|  | - | (20) I2C_DMA | 0x0 | Implementation of the DMA interface
|  | - | (19:16) I2C_NUMBER | 0x0 | I2C instance number
|  | - | (15:8) I2C_MAJOR_REVISION | 0x1 | I2C Major Revision number
|  | - | (7:0) I2C_MINOR_REVISION | 0x0 | I2C Minor Revision number