# Clock Detector and System Monitor

The clock detector is used to monitor the clocks that are crucial to proper system execution. This circuit can be used to detect the presence of these key clock signals. If required, and if the clock is missing or not toggling, this block can be configured to reset the digital portions of the device, as described in Resets.

The clock source monitored by the clock detector depends on the power mode (see Power Modes), and the state of the system power supplies in that mode. The clock detector indicates that a clock is present in the system whenever the monitored clock is at or above a minimum frequency of 4 kHz. This clock selection is automatically controlled by the underlying power-supply state machines of the RSL15 SoC, selecting the following clock sources for each mode:

System startup

RC oscillator (see RC Oscillator)

System shutdown

No clock monitored, as the system is already being reset or being held in a reset state pending recovery of a supplied voltage above the monitored minimum thresholds configured for proper system execution.

Run Mode

CPCLK (see Power Supply Clocks)

Sleep or Standby Mode

RTC clock (see Real Time Clock (RTC))

To enable resets using the clock detector, use the ACS_CLK_DET_CTRL register to perform these steps:

1. Enable the clock detector by setting the ACS_CLK_DET_CTRL_ENABLE bit.
2. Monitor the ACS_CLK_DET_CTRL_CLOCK_PRESENT bit, waiting for this flag to go high (indicating that the monitored clock is present).
3. Clear the ACS_CLK_DET_CTRL_RESET_IGNORE bit.

To disable resets caused by the clock detector, or to disable the clock detector itself, use the ACS_CLK_DET_CTRL register to perform these steps:

1. Set the ACS_CLK_DET_CTRL_RESET_IGNORE bit to prevent reset signals.
2. Disable the clock detector by clearing the ACS_CLK_DET_CTRL_ENABLE bit.

The ACS_RESET_STATUS_CLK_DET_RESET_FLAG bit from the ACS_RESET_STATUS register is used to indicate if the clock detector has triggered a reset.