# Baseband Controller

Address | Register Name | Register Write | Register Read | Default | Description
--- | --- | --- | --- | --- | ---
0x40001900 | BB_RWBBCNTL | (31) MASTER_SOFT_RST | (31) MASTER_SOFT_RST | 0x0 | Reset the complete system except registers and timing generator
|  | (30) MASTER_TGSOFT_RST | (30) MASTER_TGSOFT_RST | 0x0 | Reset the timing generator
|  | (29) REG_SOFT_RST | (29) REG_SOFT_RST | 0x0 | Reset the complete register block
|  | (28) RADIOCNTL_SOFT_RST | (28) RADIOCNTL_SOFT_RST | 0x0 | Reset the radio controller
|  | (27) SWINT_REQ | (27) SWINT_REQ | 0x0 | Force the generation of ble_sw_irq
|  | (26) RFTEST_ABORT | (26) RFTEST_ABORT | 0x0 | Abort the current RF testing defined as per CS-FORMAT
|  | (25) ADVERT_ABORT | (25) ADVERT_ABORT | 0x0 | Abort the current scan window
|  | (24) SCAN_ABORT | (24) SCAN_ABORT | 0x0 | Abort the current advertising event
|  | (20) MD_DSB | (20) MD_DSB | 0x0 | Allow a single Tx/Rx exchange whatever the MD bits are
|  | (19) SN_DSB | (19) SN_DSB | 0x0 | Disable sequence number management
|  | (18) NESN_DSB | (18) NESN_DSB | 0x0 | Disable acknowledge scheme
|  | (17) CRYPT_DSB | (17) CRYPT_DSB | 0x0 | Disable encryption/decryption
|  | (16) LRPMAP_DSB | (16) LRPMAP_DSB | 0x0 | LR pattern mapper/demapper enabled (has effect only if RW_BLE_LONG_RANGE_INST is defined)
|  | (15) LRFEC_DSB | (15) LRFEC_DSB | 0x0 | LR FEC encoder/decoder enabled (has effect only if RW_BLE_LONG_RANGE_INST is defined)
|  | (14) WHIT_DSB | (14) WHIT_DSB | 0x0 | Disable whitening
|  | (13) CRC_DSB | (13) CRC_DSB | 0x0 | Disable CRC stripping
|  | (12) HOP_REMAP_DSB | (12) HOP_REMAP_DSB | 0x0 | Disable frequency hopping remapping algorithm
|  | (11) RXCTEERR_RETX_EN | (11) RXCTEERR_RETX_EN | 0x0 | Rx CTE error detection
|  | (10) ANONYMOUS_ADVERT_FILT_EN | (10) ANONYMOUS_ADVERT_FILT_EN | 0x0 | Anonymous extended advertising filtering enable control (operate in extended active scanner and extended passive scanner modes only, and when white list is used by device filtering policy)
|  | (9) ADVERTFILT_EN | (9) ADVERTFILT_EN | 0x0 | Advertising channels error filtering enable control
|  | (8) RWBLE_EN | (8) RWBLE_EN | 0x0 | Enable RW-BLE core exchange table pre-fetch mechanism
|  | (3:0) RXWINSZDEF | (3:0) RXWINSZDEF | 0x0 | Default Rx window size in us (used when device is master connected or performs its second receipt)
0x40001904 | BB_VERSION | - | (31:24) TYP | 0xA | RW-BLE core type
|  | - | (23:16) REL | 0x0 | RW-BLE core version - major release number
|  | - | (15:8) UPG | 0x11 | RW-BLE core upgrade - upgrade number
|  | - | (7:0) BUILD | 0x0 | RW-BLE core build - build number
0x40001908 | BB_RWBLEBCONF | - | (31) DMMODE | 0x0 | RW-BLE core dual mode
|  | - | (29) WLANCOEX | 0x1 | WLAN coexistence mechanism
|  | - | (28) CORRELATOR | 0x0 | Correlator present
|  | - | (27) USERXLR | 0x0 | Long range Rx present
|  | - | (26) USETXLR | 0x1 | Long range Tx present
|  | - | (24) USEISO | 0x0 | Support of isochronous channels
|  | - | (22:16) RFIF | 0x8 | Support of the RF front-end
|  | - | (15) USEDBG | 0x1 | Diagnostic port
|  | - | (14) DECIPHER | 0x0 | AES deciphering present
|  | - | (13:8) CLK_SEL | 0x8 | Operating frequency (in MHz)
|  | - | (7) INTMODE | 0x0 | Interruption mode
|  | - | (6) BUSTYPE | 0x1 | Processor bus type
|  | - | (4:0) ADD_WIDTH | 0xE | Value of the RW_BLE_ADDRESS_WIDTH parameter concerted into binary
0x4000190C | BB_INTCNTL0 | (16) ERRORINTMSK | (16) ERRORINTMSK | 0x0 | Error interrupt mask
|  | (6) ISORXINTMSK | (6) ISORXINTMSK | 0x0 | Isochronous channel Rx interrupt mask
|  | (5) ISOTXINTMSK | (5) ISOTXINTMSK | 0x0 | Isochronous channel Tx interrupt mask
|  | (4) RXINTMSK | (4) RXINTMSK | 0x0 | Rx interrupt mask
|  | (3) TXINTMSK | (3) TXINTMSK | 0x0 | Tx interrupt mask
|  | (2) SKIPEVTINTMSK | (2) SKIPEVTINTMSK | 0x0 | Skipped event interrupt mask
|  | (1) ENDEVTINTMSK | (1) ENDEVTINTMSK | 0x1 | End of event interrupt mask
|  | (0) STARTEVTINTMSK | (0) STARTEVTINTMSK | 0x1 | Start of event interrupt mask
0x40001910 | BB_INTSTAT0 | - | (16) ERRORINTSTAT | 0x0 | Error interrupt status
0x40001914 | BB_INTACK0 | (16) ERRORINTACK | (16) ERRORINTACK | 0x0 | Error interrupt acknowledgement
0x40001918 | BB_INTCNTL1 | (30:28) CLKNINTSRMSK | (30:28) CLKNINTSRMSK | 0x0 | CLKN/half-slot interrupt sub rating mask (valid range is [0:4])
|  | (27:24) CLKNINTSRVAL | (27:24) CLKNINTSRVAL | 0x0 | CLKN/half-slot interrupt sub rating value
|  | (15) FIFOINTMSK | (15) FIFOINTMSK | 0x1 | FIFO interrupt mask
|  | (6) TIMESTAMPTGT2INTMSK | (6) TIMESTAMPTGT2INTMSK | 0x0 | Time stamp target timer 2 interrupt mask
|  | (5) TIMESTAMPTGT1INTMSK | (5) TIMESTAMPTGT1INTMSK | 0x0 | Time stamp target timer 1 interrupt mask
|  | (4) FINETGTIMINTMSK | (4) FINETGTIMINTMSK | 0x0 | Fine target timer interrupt mask
|  | (3) SWINTMSK | (3) SWINTMSK | 0x0 | SW triggered interrupt mask
|  | (2) CRYPTINTMSK | (2) CRYPTINTMSK | 0x0 | Encryption engine interrupt mask
|  | (1) SLPINTMSK | (1) SLPINTMSK | 0x1 | Sleep mode interrupt mask
|  | (0) CLKNINTMSK | (0) CLKNINTMSK | 0x1 | CLKN/half slot interrupt mask
0x4000191C | BB_INTSTAT1 | - | (15) FIFOINTSTAT | 0x0 | FIFO interrupt status
|  | - | (6) TIMESTAMPTGT2INTSTAT | 0x0 | Time stamp target timer 2 interrupt status
|  | - | (5) TIMESTAMPTGT1INTSTAT | 0x0 | Time stamp target timer 1 interrupt status
|  | - | (4) FINETGTIMINTSTAT | 0x0 | Fine target timer interrupt status
|  | - | (3) SWINTSTAT | 0x0 | SW triggered interrupt status
|  | - | (2) CRYPTINTSTAT | 0x0 | Encryption engine interrupt status
|  | - | (1) SLPINTSTAT | 0x0 | Sleep mode interrupt status
|  | - | (0) CLKNINTSTAT | 0x0 | CLKN/half slot interrupt status
0x40001920 | BB_INTACK1 | (15) FIFOINTACK | (15) FIFOINTACK | 0x0 | FIFO interrupt acknowledgement
|  | (6) TIMESTAMPTGT2INTACK | (6) TIMESTAMPTGT2INTACK | 0x0 | Time stamp target timer 2 interrupt acknowledgement
|  | (5) TIMESTAMPTGT1INTACK | (5) TIMESTAMPTGT1INTACK | 0x0 | Time stamp target timer 1 interrupt acknowledgement
|  | (4) FINETGTIMINTACK | (4) FINETGTIMINTACK | 0x0 | Fine target timer interrupt acknowledgement
|  | (3) SWINTACK | (3) SWINTACK | 0x0 | SW triggered interrupt acknowledgement
|  | (2) CRYPTINTACK | (2) CRYPTINTACK | 0x0 | Encryption engine interrupt acknowledgement
|  | (1) SLPINTACK | (1) SLPINTACK | 0x0 | Sleep mode interrupt acknowledgement
|  | (0) CLKNINTACK | (0) CLKNINTACK | 0x0 | CLKN/half slot interrupt acknowledgement
0x40001924 | BB_ACTFIFOSTAT | - | (31:28) SKIP_ET_IDX | 0x0 | Exchange table entry index of the reported skipped event (valid when SKIPACTINTSTAT is set)
|  | - | (27:24) CURRENT_ET_IDX | 0x0 | Exchange table entry index of the reported current event (valid for any set reported interrupt except SKIPACTINTSTAT)
|  | - | (15) ACTFLAG | 0x0 | Forced to 1 in BLE
|  | - | (6) ISORXINTSTAT | 0x0 | Isochronous channel Rx interrupt status
|  | - | (5) ISOTXINTSTAT | 0x0 | Isochronous channel Tx interrupt status
|  | - | (4) RXINTSTAT | 0x0 | Rx interrupt status
|  | - | (3) TXINTSTAT | 0x0 | Tx interrupt status
|  | - | (2) SKIPACTINTSTAT | 0x0 | Skipped event interrupt status
|  | - | (1) ENDACTINTSTAT | 0x0 | End of event interrupt status
|  | - | (0) STARTACTINTSTAT | 0x0 | Start of event interrupt status
0x40001928 | BB_CURRENTRXDESCPTR | (13:0) CURRENTRXDESCPTR | (13:0) CURRENTRXDESCPTR | 0x0 | Rx descriptor pointer that determines the starting point of the receive buffer chained list
0x4000192C | BB_ETPR | (13:0) ETPTR | (13:0) ETPTR | 0x0 | Exchange table pointer that determines the starting point of the exchange table
0x40001930 | BB_DEEPSLCNTL | (31) EXTWKUPDSB | (31) EXTWKUPDSB | 0x0 | External wake-up disable
|  | - | (15) DEEP_SLEEP_STAT | 0x0 | Indicator of current deep sleep clock mux status
|  | (3) DEEP_SLEEP_CORR_EN | (3) DEEP_SLEEP_CORR_EN | 0x0 | Half slot counter integer and fractional part correction (apply when system has been woken-up from deep sleep mode)
|  | (2) DEEP_SLEEP_ON | (2) DEEP_SLEEP_ON | 0x0 | RW-BLE core power mode control
|  | (1) RADIO_SLEEP_EN | (1) RADIO_SLEEP_EN | 0x0 | Control the radio module
|  | (0) OSC_SLEEP_EN | (0) OSC_SLEEP_EN | 0x0 | Control the RF high frequency crystal oscillator
0x40001934 | BB_DEEPSLWKUP | (31:0) DEEPSLTIME | (31:0) DEEPSLTIME | 0x0 | Determine the time in low_power_clk clock cycles to spend in deep sleep mode before waking-up the device
0x40001938 | BB_DEEPSLSTAT | - | (31:0) DEEPSLDUR | 0x0 | Actual duration of the last deep sleep phase measured in low_power_clk clock cycle
0x4000193C | BB_ENBPRESET | (31:21) TWEXT | (31:21) TWEXT | 0x0 | Time in low power oscillator cycles allowed for stabilization of the high frequency oscillator following an external wake-up request (signal wakeup_req)
|  | (20:10) TWOSC | (20:10) TWOSC | 0x0 | Time in low power oscillator cycles allowed for stabilization of the high frequency oscillator when the deep-sleep mode has been left due to sleep-timer expiry (DEEPSLWKUP-DEEPSLTIME])
|  | (9:0) TWRM | (9:0) TWRM | 0x0 | Time in low power oscillator cycles allowed for the radio module to leave low-power mode
0x40001940 | BB_FINECNTCORR | (9:0) FINECNTCORR | (9:0) FINECNTCORR | 0x0 | Phase correction value for the 312.5us reference counter (i.e. fine counter) in half us
0x40001944 | BB_CLKNCNTCORR | (31) ABS_DELTA | (31) ABS_DELTA | 0x0 | Determine whether CLKNCNTCORR is an absolute correction or a signed "delta" increment correction
|  | (27:0) CLKNCNTCORR | (27:0) CLKNCNTCORR | 0x0 | CLKN counter correction value
0x40001950 | BB_DIAGCNTL | (31) DIAG3_EN | (31) DIAG3_EN | 0x0 | Enable diagnostic port 3 output
|  | (30:24) DIAG3 | (30:24) DIAG3 | 0x0 | Selection of the outputs that must be driven to the diagnostic port 3
|  | (23) DIAG2_EN | (23) DIAG2_EN | 0x0 | Enable diagnostic port 2 output
|  | (22:16) DIAG2 | (22:16) DIAG2 | 0x0 | Selection of the outputs that must be driven to the diagnostic port 2
|  | (15) DIAG1_EN | (15) DIAG1_EN | 0x0 | Enable diagnostic port 1 output
|  | (14:8) DIAG1 | (14:8) DIAG1 | 0x0 | Selection of the outputs that must be driven to the diagnostic port 1
|  | (7) DIAG0_EN | (7) DIAG0_EN | 0x0 | Enable diagnostic port 0 output
|  | (6:0) DIAG0 | (6:0) DIAG0 | 0x0 | Selection of the outputs that must be driven to the diagnostic port 1
0x40001954 | BB_DIAGSTAT | - | (31:24) DIAG3STAT | 0x0 | Directly connected to ble_dbg3[7:0] output (debug use only)
|  | - | (23:16) DIAG2STAT | 0x0 | Directly connected to ble_dbg2[7:0] output (debug use only)
|  | - | (15:8) DIAG1STAT | 0x0 | Directly connected to ble_dbg1[7:0] output (debug use only)
|  | - | (7:0) DIAG0STAT | 0x0 | Directly connected to ble_dbg0[7:0] output (debug use only)
0x40001958 | BB_DEBUGADDMAX | (31:16) REG_ADDMAX | (31:16) REG_ADDMAX | 0x0 | Upper limit for the register zone indicated by the reg_inzone flag
|  | (15:0) EM_ADDMAX | (15:0) EM_ADDMAX | 0x0 | Upper limit for the exchange memory zone indicated by the em_inzone flag
0x4000195C | BB_DEBUGADDMIN | (31:16) REG_ADDMIN | (31:16) REG_ADDMIN | 0x0 | Lower limit for the register zone indicated by the reg_inzone flag
|  | (15:0) EM_ADDMIN | (15:0) EM_ADDMIN | 0x0 | Lower limit for the exchange memory zone indicated by the em_inzone flag
0x40001960 | BB_ERRORTYPESTAT | - | (22) DFCNTL_EMACC_ERROR | 0x0 | Indicate that direction finding controller has an EM Access error (happen when exchange memory accesses are not served in time and data are corrupted)
|  | - | (21) FIFOINTOVF | 0x0 | Indicate that the FIFO IRQ is overflowed
|  | - | (20) PHY_ERROR | 0x0 | Indicate that the programmed CS-AUX/TX/RX-RATE fields are not matching the RADIOCNTL2-PHYMSK fields indicating which PHY the radio is currently supporting
|  | - | (19) TXAEHEADER_PTR_ERROR | 0x0 | Indicate Tx pointer to the extended advertising packet that has to be sent is null, while the extended header length is not null and the packet to be sent is an extended advertising packet
|  | - | (18) TMAFS_ERROR | 0x0 | Indicate T_MAFS is smaller than 300us in between a transmitted advertising packet containing an AuxPtr field and its chained packet (this comes from bad settings of Aux_Offset and/or Offset_Unit values)
|  | - | (17) RAL_UNDERRUN | 0x0 | Indicate resolving address list engine under run issue (happen when RAL List parsing not finished on time)
|  | - | (16) RAL_ERROR | 0x0 | Indicate resolving address list engine faced a bad setting
|  | - | (15) RXDATA_PTR_ERROR | 0x0 | Indicate whether Rx data buffer pointer value programmed is null (major failure)
|  | - | (14) TXDATA_PTR_ERROR | 0x0 | Indicate whether Tx data buffer pointer value programmed is null during advertising/scanning/initiating events, or during master/slave connections with non-null packet length (major failure)
|  | - | (13) RXDESC_EMPTY_ERROR | 0x0 | Indicate whether Rx descriptor pointer value programmed in register is null (major failure)
|  | - | (12) TXDESC_EMPTY_ERROR | 0x0 | Indicate whether Tx descriptor pointer value programmed in control structure is null during advertising/scanning/initiating events (major failure)
|  | - | (11) CSFORMAT_ERROR | 0x0 | Indicate whether CS-FORMAT has been programmed with an invalid value (major failure)
|  | - | (10) LLCHMAP_ERROR | 0x0 | Indicate link layer channel map error (happen when actual number of CS-LLCHMAP bit set to one is different from CS-NBCHGOOD at the beginning of frequency hopping process)
|  | - | (9) ADV_UNDERRUN | 0x0 | Indicate advertising interval under run
|  | - | (8) IFS_UNDERRUN | 0x0 | Indicate inter frame space under run (occur if IFS time is not enough to update and read control structure/descriptors, and/or white list parsing is not finished and/or decryption time is too long to be finished on time)
|  | - | (7) LIST_ERROR | 0x0 | Indicate a software programming issue (white list or periodic advertiser list or ADI list search request with empty list, or null base pointer)
|  | - | (6) EVT_CNTL_APFM_ERROR | 0x0 | Indicate anticipated pre-fetch mechanism error (happen when 2 consecutive events are programmed, and when the first event is not completely finished while second pre-fetch instant is reached)
|  | - | (5) ACT_SCHDL_APFM_ERROR | 0x0 | Indicate anticipated pre-fetch mechanism error (happen when 2 consecutive events are programmed, and when the first event is not completely finished while second pre-fetch instant is reached)
|  | - | (4) ACT_SCHDL_ENTRY_ERROR | 0x0 | Indicate activity scheduler faced Invalid timing programing on two consecutive ET entries
|  | - | (3) RADIO_EMACC_ERROR | 0x0 | Indicate radio controller exchange memory access error (happen when exchange memory accesses are not served in time and data are corrupted)
|  | - | (2) PKTCNTL_EMACC_ERROR | 0x0 | Indicate packet controller exchange memory access error (happen when exchange memory accesses are not served in time and Tx/Rx data are corrupted)
|  | - | (1) RXCRYPT_ERROR | 0x0 | Indicate real time decryption error (happen when AES-CCM decryption is too slow compared to packet controller requests)
|  | - | (0) TXCRYPT_ERROR | 0x0 | Indicate real time encryption error (happen when AES-CCM encryption is too slow compared to packet controller requests)
0x40001964 | BB_SWPROFILING | (31:0) SWPROF | (31:0) SWPROF | 0x0 | Software profiling register (used by RW-BLE software for profiling purpose)
0x40001970 | BB_RADIOCNTL0 | (29:16) SPIPTR | (29:16) SPIPTR | 0x0 | Pointer to the buffer containing data to be transferred to or received from the SPI port
|  | (7) SPICFG | (7) SPICFG | 0x0 | SPI configuration/used for SW-driven access and SPI structure interpretation (interpretation is radio dependent)
|  | (5:4) SPIFREQ | (5:4) SPIFREQ | 0x0 | SPI clock frequency
|  | - | (1) SPICOMP | 0x1 | SPI transfer status
|  | (0) SPIGO | (0) SPIGO | 0x0 | Start SPI transfer when writing a 1
0x40001974 | BB_RADIOCNTL1 | (31) FORCEAGC_EN | (31) FORCEAGC_EN | 0x0 | Control AGC force mode based onto FORCEAGC_LENGTH value
|  | (30) FORCEIQ | (30) FORCEIQ | 0x0 | Control modulation mode in between FM and I and Q
|  | (29) RXDNSL | (29) RXDNSL | 0x0 | Do not send length (over SPI) during Rx operation
|  | (28) TXDNSL | (28) TXDNSL | 0x0 | Do not send length (over SPI) during Tx operation
|  | (27:16) FORCEAGC_LENGTH | (27:16) FORCEAGC_LENGTH | 0x0 | Control ATLAS/Ripple AGC force mode based on radioCNTL2-FORCEAGC_LENGTH value
|  | (15) SYNC_PULSE_MODE | (15) SYNC_PULSE_MODE | 0x0 | Define whether the SYNC_P pulse is generated as pulse or level
|  | (14) SYNC_PULSE_SRC | (14) SYNC_PULSE_SRC | 0x0 | Define whether access address synchronization detection is generated internally or comes from the radio
|  | (13) DPCORR_EN | (13) DPCORR_EN | 0x0 | Enable the use of delayed DC compensated data path in radio correlator block
|  | (12) JEF_SELECT | (12) JEF_SELECT | 0x0 | Select jitter elimination FIFO
|  | (9:4) XRFSEL | (9:4) XRFSEL | 0x0 | Extended radio selection field
|  | (3:0) SUBVERSION | (3:0) SUBVERSION | 0x0 | CSEM RF sub-version selection
0x40001978 | BB_RADIOCNTL2 | (31:30) LRSYNCCOMPMODE | (31:30) LRSYNCCOMPMODE | 0x3 | Long-range synchronization compensation operating mode
|  | (29) RXCITERMBYPASS | (29) RXCITERMBYPASS | 0x0 | Long-range CI bit[1] and TERM1 bypass mode (allow to receive only CI bit 0 and then wait for Rx payload directly)
|  | (28:24) LRVTBFLUSH | (28:24) LRVTBFLUSH | 0x8 | Indicate long range Viterbi flush instant (this value corresponds to the Viterbi trace back depth used in the selected design, hence corresponding to the number of remaining samples flush out just before the end of the packet)
|  | (23:22) PHYMSK | (23:22) PHYMSK | 0x0 | Indicate selected radio PHY support capabilities (in addition to 1Mbps that is mandatory)
|  | (21:20) LRSYNCERR | (21:20) LRSYNCERR | 0x0 | Number of errors allowed during long range Rx stream detection (when performed internally)
|  | (18:16) SYNCERR | (18:16) SYNCERR | 0x0 | Indicate the maximum number of errors allowed to recognize the synchronization word
|  | (13:0) FREQTABLE_PTR | (13:0) FREQTABLE_PTR | 0x40 | Frequency table pointer
0x4000197C | BB_RADIOCNTL3 | (31:30) RXRATE3CFG | (31:30) RXRATE3CFG | 0x3 | Rate out programmable value in Rx when CS-RXRATE is set to 0x3 (i.e 500kbps Long range)
|  | (29:28) RXRATE2CFG | (29:28) RXRATE2CFG | 0x2 | Rate out programmable value in Rx when CS-RXRATE is set to 0x2 (i.e 125kbps Long range)
|  | (27:26) RXRATE1CFG | (27:26) RXRATE1CFG | 0x1 | Rate out programmable value in Rx when CS-RXRATE is set to 0x1 (i.e 2Mbps)
|  | (25:24) RXRATE0CFG | (25:24) RXRATE0CFG | 0x0 | Rate out programmable value in Rx when CS-RXRATE is set to 0x0 (i.e 1Mbps)
|  | (22:20) GETRSSIDELAY | (22:20) GETRSSIDELAY | 0x4 | Delay to read RSSI after an RSSI read request
|  | (18) RXSYNC_ROUTING | (18) RXSYNC_ROUTING | 0x0 | Access address detection information routing
|  | (17:16) RXVALID_BEH | (17:16) RXVALID_BEH | 0x0 | Define radio_in[3] expected behavior
|  | (15:14) TXRATE3CFG | (15:14) TXRATE3CFG | 0x3 | Rate out programmable value in Tx when CS-TX/AUX-RATE is set to 0x3 (i.e 500kbps Long range)
|  | (13:12) TXRATE2CFG | (13:12) TXRATE2CFG | 0x2 | Rate out programmable value in Tx when CS-TX/AUX-RATE is set to 0x2 (i.e 125kbps Long range)
|  | (11:10) TXRATE1CFG | (11:10) TXRATE1CFG | 0x1 | Rate out programmable value in Tx when CS-TX/AUX-RATE is set to 0x1 (i.e 2Mbps)
|  | (9:8) TXRATE0CFG | (9:8) TXRATE0CFG | 0x0 | Rate out programmable value in Tx when CS-TX/AUX-RATE is set to 0x0 (i.e 1Mbps)
|  | (1:0) TXVALID_BEH | (1:0) TXVALID_BEH | 0x0 | Define radio_out [3] expected behavior
0x40001980 | BB_RADIOPWRUPDN0 | (31:24) SYNC_POSITION0 | (31:24) SYNC_POSITION0 | 0x0 | Access address detection pulse/level position for uncoded PHY at 1Mbps
|  | (23:16) RXPWRUP0 | (23:16) RXPWRUP0 | 0x0 | Radio Rx power up (in us) for uncoded PHY at 1Mbps
|  | (14:8) TXPWRDN0 | (14:8) TXPWRDN0 | 0x0 | Radio Tx power down (in us) for uncoded PHY at 1Mbps
|  | (7:0) TXPWRUP0 | (7:0) TXPWRUP0 | 0x0 | Radio Tx power up (in us) for uncoded PHY at 1Mbps
0x40001984 | BB_RADIOPWRUPDN1 | (31:24) SYNC_POSITION1 | (31:24) SYNC_POSITION1 | 0x0 | Access address detection pulse/level position for uncoded PHY at 2Mbps
|  | (23:16) RXPWRUP1 | (23:16) RXPWRUP1 | 0x0 | Radio Rx power up (in us) for uncoded PHY at 2Mbps
|  | (14:8) TXPWRDN1 | (14:8) TXPWRDN1 | 0x0 | Radio Tx power down (in us) for uncoded PHY at 2Mbps
|  | (7:0) TXPWRUP1 | (7:0) TXPWRUP1 | 0x0 | Radio Tx power up (in us) for uncoded PHY at 2Mbps
0x40001988 | BB_RADIOPWRUPDN2 | (31:24) SYNC_POSITION2 | (31:24) SYNC_POSITION2 | 0x0 | Access address detection pulse/level position for coded PHY at 125kbps
|  | (23:16) RXPWRUP2 | (23:16) RXPWRUP2 | 0x0 | Radio Rx power up (in us) for coded PHY at 125kbps
|  | (14:8) TXPWRDN2 | (14:8) TXPWRDN2 | 0x0 | Radio Tx power down (in us) for coded PHY at 125kbps
|  | (7:0) TXPWRUP2 | (7:0) TXPWRUP2 | 0x0 | Radio Tx power up (in us) for coded PHY at 125kbps
0x4000198C | BB_RADIOPWRUPDN3 | (14:8) TXPWRDN3 | (14:8) TXPWRDN3 | 0x0 | Radio Tx power down (in us) for coded PHY at 500kbps
|  | (7:0) TXPWRUP3 | (7:0) TXPWRUP3 | 0x0 | Radio Tx power up for (in us) PHY at 500kbps
0x40001990 | BB_RADIOTXRXTIM0 | (22:16) RFRXTMDA0 | (22:16) RFRXTMDA0 | 0x0 | RF Rx test mode delay adjustment for uncoded PHY at 1Mbps
|  | (14:8) RXPATHDLY0 | (14:8) RXPATHDLY0 | 0x0 | Rx path delay (in us) for uncoded PHY at 1Mbps
|  | (6:0) TXPATHDLY0 | (6:0) TXPATHDLY0 | 0x0 | Rx path delay (in us) for uncoded PHY at 1Mbps
0x40001994 | BB_RADIOTXRXTIM1 | (22:16) RFRXTMDA1 | (22:16) RFRXTMDA1 | 0x0 | RF Rx test mode delay adjustment for uncoded PHY at 2Mbps
|  | (14:8) RXPATHDLY1 | (14:8) RXPATHDLY1 | 0x0 | Rx path delay (in us) for uncoded PHY at 2Mbps
|  | (6:0) TXPATHDLY1 | (6:0) TXPATHDLY1 | 0x0 | Rx path delay (in us) for uncoded PHY at 2Mbps
0x40001998 | BB_RADIOTXRXTIM2 | (31:24) RXFLUSHPATHDLY2 | (31:24) RXFLUSHPATHDLY2 | 0x0 | Rx path delay (in us) for coded PHY at 125kbps
|  | (23:16) RFRXTMDA2 | (23:16) RFRXTMDA2 | 0x0 | RF Rx test mode delay adjustment for uncoded PHY at 125kbps
|  | (15:8) RXPATHDLY2 | (15:8) RXPATHDLY2 | 0x0 | Rx path delay (in us) for uncoded PHY at 125kbps
|  | (6:0) TXPATHDLY2 | (6:0) TXPATHDLY2 | 0x0 | Rx path delay (in us) for uncoded PHY at 125kbps
0x4000199C | BB_RADIOTXRXTIM3 | (31:24) RXFLUSHPATHDLY3 | (31:24) RXFLUSHPATHDLY3 | 0x0 | Rx path delay (in us) for coded PHY at 500kbps
|  | (22:16) RFRXTMDA3 | (22:16) RFRXTMDA3 | 0x0 | RF Rx test mode delay adjustment for coded PHY at 500kbps
|  | (6:0) TXPATHDLY3 | (6:0) TXPATHDLY3 | 0x0 | Rx path delay (in us) for coded PHY at 500kbps
0x400019A0 | BB_SPIPTRCNTL0 | (29:16) TXOFFPTR | (29:16) TXOFFPTR | 0x0 | Pointer to the TxOFF sequence address section
|  | (13:0) TXONPTR | (13:0) TXONPTR | 0x0 | Pointer to the TxON sequence address section
0x400019A4 | BB_SPIPTRCNTL1 | (29:16) RXOFFPTR | (29:16) RXOFFPTR | 0x0 | Pointer to the RxOFF sequence address section
|  | (13:0) RXONPTR | (13:0) RXONPTR | 0x0 | Pointer to the RxON sequence address section
0x400019A8 | BB_SPIPTRCNTL2 | (29:16) RXLENGTHPTR | (29:16) RXLENGTHPTR | 0x0 | Pointer to the received length write sequence address section
|  | (13:0) RSSIPTR | (13:0) RSSIPTR | 0x0 | Pointer to the RSSI read sequence address section
0x400019AC | BB_SPIPTRCNTL3 | (29:16) CTESAMPPTR | (29:16) CTESAMPPTR | 0x0 | Pointer to the CTE sampling indication sequence address section
|  | (13:0) RXPKTTYPPTR | (13:0) RXPKTTYPPTR | 0x0 | Pointer to the received packet type indication sequence address section
0x400019B0 | BB_AESCNTL | (1) AES_MODE | (1) AES_MODE | 0x0 | Cipher mode control
|  | (0) AES_START | (0) AES_START | 0x0 | Start AES-128 ciphering/deciphering process
0x400019B4 | BB_AESKEY31_0 | (31:0) AESKEY31_0 | (31:0) AESKEY31_0 | 0x0 | AES encryption 128-bit key (bits 31 down to 0)
0x400019B8 | BB_AESKEY63_32 | (31:0) AESKEY63_32 | (31:0) AESKEY63_32 | 0x0 | AES encryption 128-bit key (bits 63 down to 32)
0x400019BC | BB_AESKEY95_64 | (31:0) AESKEY95_64 | (31:0) AESKEY95_64 | 0x0 | AES encryption 128-bit key (bits 95 down to 64)
0x400019C0 | BB_AESKEY127_96 | (31:0) AESKEY127_96 | (31:0) AESKEY127_96 | 0x0 | AES encryption 128-bit key (bits 127 down to 96)
0x400019C4 | BB_AESPTR | (13:0) AESPTR | (13:0) AESPTR | 0x0 | Pointer to the memory zone where the block to cipher/decipher using AES-128 is stored
0x400019C8 | BB_TXMICVAL | - | (31:0) TXMICVAL | 0x0 | AES-CCM plain MIC value (valid on when MIC has been calculated in Tx)
0x400019CC | BB_RXMICVAL | - | (31:0) RXMICVAL | 0x0 | AES-CCM plain MIC value (valid on once MIC has been extracted from Rx packet)
0x400019D0 | BB_RFTESTCNTL | (31) INFINITERX | (31) INFINITERX | 0x0 | Applicable in RF test mode only
|  | (27) RXPKTCNTEN | (27) RXPKTCNTEN | 0x0 | Applicable in RF test mode only
|  | (25:24) PERCOUNT_MODE | (25:24) PERCOUNT_MODE | 0x0 | Applicable in RF direct Rx test mode only, and when RXPKTCNTEN equals to 1
|  | (15) INFINITETX | (15) INFINITETX | 0x0 | Applicable in RF test mode only
|  | (14) TXLENGTHSRC | (14) TXLENGTHSRC | 0x0 | Applicable only in Tx/Rx RF test mode
|  | (13) PRBSTYPE | (13) PRBSTYPE | 0x0 | Applicable only in Tx/Rx RF test mode
|  | (12) TXPLDSRC | (12) TXPLDSRC | 0x0 | Applicable only in Tx/Rx RF test mode
|  | (11) TXPKTCNTEN | (11) TXPKTCNTEN | 0x0 | Applicable in RF test mode only
|  | (7:0) TXLENGTH | (7:0) TXLENGTH | 0x0 | Tx packet length in number of byte
0x400019D4 | BB_RFTESTTXSTAT | - | (31:0) TXPKTCNT | 0x0 | Report number of transmitted packet during test modes
0x400019D8 | BB_RFTESTRXSTAT | - | (31:0) RXPKTCNT | 0x0 | Report number of correctly received packet during test modes
0x400019E0 | BB_TIMGENCNTL | (25:16) PREFETCHABORT_TIME | (25:16) PREFETCHABORT_TIME | 0x1FE | Define the instant in us at which immediate abort is required after anticipated pre-fetch abort
|  | (8:0) PREFETCH_TIME | (8:0) PREFETCH_TIME | 0x96 | Define exchange table pre-fetch instant in us
0x400019E4 | BB_FINETIMTGT | (27:0) FINETARGET | (27:0) FINETARGET | 0x0 | Fine timer target value on which a ble_finetgtim_irq must be generated (this timer has a precision of 312.5us and interrupt is generated only when FINETARGET = CLKN)
0x400019E8 | BB_CLKNTGT1 | (27:0) CLKNTGT1 | (27:0) CLKNTGT1 | 0x0 | This timer has a precision of 312.5us (interrupt is generated only when CLKNTGT = CLKN and HMICROSECTGT = FINECNT)
0x400019EC | BB_HMICROSECTGT1 | (9:0) HMICROSECTGT1 | (9:0) HMICROSECTGT1 | 0x0 | This timer has a precision of 0.5us (interrupt is generated only when CLKNTGT = CLKN and HMICROSECTGT = FINECNT)
0x400019F0 | BB_CLKNTGT2 | (27:0) CLKNTGT2 | (27:0) CLKNTGT2 | 0x0 | This timer has a precision of 312.5us (interrupt is generated only when CLKNTGT = CLKN and HMICROSECTGT = FINECNT)
0x400019F4 | BB_HMICROSECTGT2 | (9:0) HMICROSECTGT2 | (9:0) HMICROSECTGT2 | 0x0 | This timer has a precision of 0.5us (interrupt is generated only when CLKNTGT = CLKN and HMICROSECTGT = FINECNT)
0x400019F8 | BB_SLOTCLK | (31) SAMP | (31) SAMP | 0x0 | Sample the CLKN counter value in SCLK register field
|  | (30) CLKN_UPD | (30) CLKN_UPD | 0x0 | Update CLKN counter
|  | (27:0) SCLK | (27:0) SCLK | 0x0 | Value of the 312.5us CLKN counter
0x400019FC | BB_FINETIMECNT | - | (9:0) FINECNT | 0x0 | This timer has a precision of 0.5us (interrupt is generated only when CLKNTGT = CLKN and HMICROSECTGT = FINECNT)
0x40001A00 | BB_ACTSCHCNTL | (31) START_ACT | (31) START_ACT | 0x0 | Request the RW-BLE core to start an event
|  | (3:0) ENTRY_IDX | (3:0) ENTRY_IDX | 0x0 | Indicate the activity scheduler entry index which has to be used when START_ACT is set
0x40001A04 | BB_STARTEVTCLKNTS | - | (27:0) STARTEVTCLKNTS | 0x0 | Value of the CLKN counter when ble_start_int is generated
0x40001A08 | BB_STARTEVTFINECNTTS | - | (9:0) STARTEVTFINECNTTS | 0x0 | Value of the fine counter when ble_start_int is generated
0x40001A0C | BB_ENDEVTCLKNTS | - | (27:0) ENDEVTCLKNTS | 0x0 | Value of the CLKN counter when ble_end_int is generated
0x40001A10 | BB_ENDEVTFINECNTTS | - | (9:0) ENDEVTFINECNTTS | 0x0 | Value of the fine counter when ble_end_int is generated
0x40001A14 | BB_SKIPEVTCLKNTS | - | (27:0) SKIPEVTCLKNTS | 0x0 | Value of the CLKN counter when ble_skip_int is generated
0x40001A18 | BB_SKIPEVTFINECNTTS | - | (9:0) SKIPEVTFINECNTTS | 0x0 | Value of the fine counter when ble_skip_int is generated
0x40001A20 | BB_ADVTIM | (31:24) TX_AUXPTR_THR | (31:24) TX_AUXPTR_THR | 0x0 | Extended advertising AuxPtr threshold value in Tx (granularity 16us)
|  | (23:16) RX_AUXPTR_THR | (23:16) RX_AUXPTR_THR | 0x0 | Extended advertising AuxPtr threshold value in Rx (granularity 16us)
|  | (13:0) ADVINT | (13:0) ADVINT | 0x0 | Advertising packet interval defining the time interval in between two ADV_xxx packet sent (value in us)
0x40001A24 | BB_ACTSCANCNTL | (24:16) BACKOFF | (24:16) BACKOFF | 0x1 | Active scan mode back-off counter initialization value
|  | (8:0) UPPERLIMIT | (8:0) UPPERLIMIT | 0x1 | Active scan mode upper limit counter value
0x40001A30 | BB_WPALCNTL | (23:16) WPALNBDEV | (23:16) WPALNBDEV | 0x0 | Number of devices in the white list
|  | (13:0) WPALBASEPTR | (13:0) WPALBASEPTR | 0x0 | Base address pointer of the white list
0x40001A34 | BB_WPALCURRENPTR | (13:0) WPALCURRENPTR | (13:0) WPALCURRENPTR | 0x0 | Current pointer in use for the white list
0x40001A38 | BB_SEARCH_TIMEOUT | (5:0) SEARCH_TIMEOUT | (5:0) SEARCH_TIMEOUT | 0x10 | RAL and list search engines timeout delay in us
0x40001A40 | BB_COEXIFCNTL0 | (21:20) MWSSCANFREQMSK | (21:20) MWSSCANFREQMSK | 0x0 | Determine how mws_scan_frequency impacts BLE Tx and Rx
|  | (19:18) WLCRXPRIOMODE | (19:18) WLCRXPRIOMODE | 0x0 | Define BLE packet ble_rx mode behavior
|  | (17:16) WLCTXPRIOMODE | (17:16) WLCTXPRIOMODE | 0x0 | Define BLE packet ble_tx mode behavior
|  | (15:14) MWSTXFREQMSK | (15:14) MWSTXFREQMSK | 0x0 | Determine how MWS Tx Frequency impacts BLE Tx and Rx
|  | (13:12) MWSRXFREQMSK | (13:12) MWSRXFREQMSK | 0x0 | Determine how MWS Rx frequency impacts BLE Tx and Rx
|  | (11:10) MWSTXMSK | (11:10) MWSTXMSK | 0x0 | Determine how mws_tx impacts BLE Tx and Rx
|  | (9:8) MWSRXMSK | (9:8) MWSRXMSK | 0x0 | Determine how mws_rx impacts BLE Tx and Rx
|  | (7:6) WLANTXMSK | (7:6) WLANTXMSK | 0x0 | Determine how wlan_tx impacts BLE Tx and Rx
|  | (5:4) WLANRXMSK | (5:4) WLANRXMSK | 0x1 | Determine how wlan_rx impacts BLE Tx and Rx
|  | (3) MWSWCI_EN | (3) MWSWCI_EN | 0x0 | Enable/disable control of the WCI MWS coexistence interface (valid in dual mode only)
|  | (2) MWSCOEX_EN | (2) MWSCOEX_EN | 0x0 | Enable/disable control of the MWS Coexistence control (valid in dual mode only)
|  | (1) SYNCGEN_EN | (1) SYNCGEN_EN | 0x0 | Determine whether ble_sync is generated or not
|  | (0) WLANCOEX_EN | (0) WLANCOEX_EN | 0x0 | Enable/disable control of the MWS/WLAN coexistence control
0x40001A44 | BB_COEXIFCNTL1 | (28:24) WLCPRXTHR | (28:24) WLCPRXTHR | 0x0 | Determine the threshold for Rx priority setting (apply on ble_rx if WLCRXPRIOMODE equals "10")
|  | (20:16) WLCPTXTHR | (20:16) WLCPTXTHR | 0x0 | Determine the threshold for priority setting (apply on ble_tx if WLCTXPRIOMODE equals "10")
|  | (14:8) WLCPDURATION | (14:8) WLCPDURATION | 0x0 | Determine how many us the priority information must be maintained (apply on ble_tx and ble_rx if WLCTXPRIOMODE and WLCRXPRIOMODE equal "10")
|  | (6:0) WLCPDELAY | (6:0) WLCPDELAY | 0x0 | Determine the delay (in us) in Tx/Rx enables rises the time BLE Tx/Rx priority has to be provided (apply on ble_tx and ble_rx if WLCTXPRIOMODE and WLCRXPRIOMODE equal "10")
0x40001A48 | BB_COEXIFCNTL2 | (11:8) RX_ANT_DELAY | (11:8) RX_ANT_DELAY | 0x0 | Time (in us) by which is anticipated bt_rx to be provided before effective radio receipt operation
|  | (3:0) TX_ANT_DELAY | (3:0) TX_ANT_DELAY | 0x0 | Time (in us) by which is anticipated bt_tx to be provided before effective radio transmit operation
0x40001A4C | BB_BLEMPRIO0 | (31:28) BLEM7 | (31:28) BLEM7 | 0x3 | Set priority value for passive scanning
|  | (27:24) BLEM6 | (27:24) BLEM6 | 0x4 | Set priority value for non-connectable advertising
|  | (23:20) BLEM5 | (23:20) BLEM5 | 0x8 | Set priority value for connectable advertising BLE message
|  | (19:16) BLEM4 | (19:16) BLEM4 | 0x9 | Set priority value for active scanning BLE message
|  | (15:12) BLEM3 | (15:12) BLEM3 | 0xA | Set priority value for initiating (scanning) BLE message
|  | (11:8) BLEM2 | (11:8) BLEM2 | 0xD | Set priority value for data channel transmission BLE message
|  | (7:4) BLEM1 | (7:4) BLEM1 | 0xE | Set priority value for LLCP BLE message
|  | (3:0) BLEM0 | (3:0) BLEM0 | 0xF | Set priority value for initiating (connection request response) BLE message
0x40001A50 | BB_BLEMPRIO1 | (31:28) BLEM15 | (31:28) BLEM15 | 0x3 | Set priority value for passive extended passive scanning on secondary advertising channels
|  | (27:24) BLEM14 | (27:24) BLEM14 | 0x4 | Set priority value for non-connectable extended advertising on secondary advertising channels
|  | (23:20) BLEM13 | (23:20) BLEM13 | 0x8 | Set priority value for connectable extended advertising on secondary advertising channels
|  | (19:16) BLEM12 | (19:16) BLEM12 | 0x9 | Set priority value for extended active scanning on secondary advertising channels
|  | (15:12) BLEM11 | (15:12) BLEM11 | 0xA | Set priority value for extended initiating on secondary advertising channels
|  | (11:8) BLEM10 | (11:8) BLEM10 | 0xF | Set priority value for connection establishment BLE message on secondary advertising channels
|  | (7:4) BLEM9 | (7:4) BLEM9 | 0xD | Set default priority value for ISO channel subsequent Tx/Rx attempt
|  | (3:0) BLEM8 | (3:0) BLEM8 | 0xC | Set default priority value for ISO channel first Tx/Rx attempt
0x40001A54 | BB_BLEMPRIO2 | (31:28) BLEMDEFAULT | (31:28) BLEMDEFAULT | 0x3 | Set priority value for extended initiating on secondary advertising channels
|  | (11:8) BLEM18 | (11:8) BLEM18 | 0x2 | Set priority value for connection establishment BLE message on secondary advertising channels
|  | (7:4) BLEM17 | (7:4) BLEM17 | 0x7 | Set default priority value for ISO channel subsequent Tx/Rx attempt
|  | (3:0) BLEM16 | (3:0) BLEM16 | 0x7 | Set default priority value for ISO channel first Tx/Rx attempt
0x40001A60 | BB_RALCNTL | (23:16) RALNBDEV | (23:16) RALNBDEV | 0x0 | Number of devices in RAL structure
|  | (13:0) RALBASEPTR | (13:0) RALBASEPTR | 0x0 | Start address pointer of the RAL structure
0x40001A64 | BB_RALCURRENTPTR | (13:0) RALCURRENTPTR | (13:0) RALCURRENTPTR | 0x0 | Current pointer of the RAL structure
0x40001A68 | BB_RAL_LOCAL_RND | (31) LRND_INIT | (31) LRND_INIT | 0x0 | Writing a 1 initializes of local RPA random number generation LFSR
|  | (21:0) LRND_VAL | (21:0) LRND_VAL | 0x3F0F0F | Initialization value for local RPA random generation when LRDN_INIT is set to 1 (report the current local RPA random number LFSR value otherwise)
0x40001A6C | BB_RAL_PEER_RND | (31) PRND_INIT | (31) PRND_INIT | 0x0 | Writing a 1 initializes of peer RPA random number generation LFSR
|  | (21:0) PRND_VAL | (21:0) PRND_VAL | 0x30F0F0 | Initialization value for peer RPA random generation when LRDN_INIT is set to 1 (report the current local RPA random number LFSR value otherwise)
0x40001A70 | BB_DFCNTL0_1US | (31:24) RXSAMPSTINST0_1US | (31:24) RXSAMPSTINST0_1US | 0x0 | Adjustement delay in half us of Rx I and Q sampling start instant for LE 1M PHY (with 1us sampling interval)
|  | (23:16) RXSWSTINST0_1US | (23:16) RXSWSTINST0_1US | 0x0 | Adjustement delay in half us of Rx switch start instant for LE 1M PHY (with 1us switching interval)
|  | (7:0) TXSWSTINST0_1US | (7:0) TXSWSTINST0_1US | 0x0 | Adjustement delay in half us of Tx switch start instant for LE 1M PHY (with 1us switching interval)
0x40001A74 | BB_DFCNTL0_2US | (31:24) RXSAMPSTINST0_2US | (31:24) RXSAMPSTINST0_2US | 0x0 | Adjustement delay in half us of Rx I and Q sampling start instant for LE 1M PHY (with 2us sampling interval)
|  | (23:16) RXSWSTINST0_2US | (23:16) RXSWSTINST0_2US | 0x0 | Adjustement delay in half us of Rx switch start instant for LE 1M PHY (with 2us switching interval)
|  | (7:0) TXSWSTINST0_2US | (7:0) TXSWSTINST0_2US | 0x0 | Adjustement delay in half us of Tx switch start instant for LE 1M PHY (with 2us switching interval)
0x40001A78 | BB_DFCNTL1_1US | (31:24) RXSAMPSTINST1_1US | (31:24) RXSAMPSTINST1_1US | 0x0 | Adjustement delay in half us of Rx I and Q sampling start instant for LE 2M PHY (with 1us sampling interval)
|  | (23:16) RXSWSTINST1_1US | (23:16) RXSWSTINST1_1US | 0x0 | Adjustement delay in half us of Rx switch start instant for LE 2M PHY (with 1us switching interval)
|  | (7:0) TXSWSTINST1_1US | (7:0) TXSWSTINST1_1US | 0x0 | Adjustement delay in half us of Tx switch start instant for LE 2M PHY (with 1us switching interval)
0x40001A7C | BB_DFCNTL1_2US | (31:24) RXSAMPSTINST1_2US | (31:24) RXSAMPSTINST1_2US | 0x0 | Adjustement delay in half us of Rx I and Q sampling start instant for LE 2M PHY (with 2us sampling interval)
|  | (23:16) RXSWSTINST1_2US | (23:16) RXSWSTINST1_2US | 0x0 | Adjustement delay in half us of Rx switch start instant for LE 2M PHY (with 2us switching interval)
|  | (7:0) TXSWSTINST1_2US | (7:0) TXSWSTINST1_2US | 0x0 | Adjustement delay in half us of Tx switch start instant for LE 2M PHY (with 2us switching interval)
0x40001A80 | BB_DFCURRENTPTR | (13:0) DFCURRENTPTR | (13:0) DFCURRENTPTR | 0x0 | Rx CTE descriptor current pointer
0x40001A84 | BB_DFANTCNTL | (15) RXPRIMIDCNTLEN | (15) RXPRIMIDCNTLEN | 0x0 | Reception primary antenna ID enable control
|  | (14:8) RXPRIMANTID | (14:8) RXPRIMANTID | 0x0 | Primary antenna ID to be used on each Rx start instant
|  | (7) TXPRIMIDCNTLEN | (7) TXPRIMIDCNTLEN | 0x0 | Transmit primary antenna ID enable control
|  | (6:0) TXPRIMANTID | (6:0) TXPRIMANTID | 0x0 | Primary antenna ID to be used on each Tx start instant
0x40001A88 | BB_DFIFCNTL | (7) ANTSWITCH_BEH | (7) ANTSWITCH_BEH | 0x0 | Define the antenna switch qualifier behavior
|  | (6) SAMPREQ_BEH | (6) SAMPREQ_BEH | 0x0 | Define the I and Q sampling request behavior
|  | (5:4) SAMPVALID_BEH | (5:4) SAMPVALID_BEH | 0x3 | Define the I and Q sample qualifier behavior
|  | (3:2) IF_WIDTH | (3:2) IF_WIDTH | 0x3 | Define the I and Q sample interface width
|  | (1) MSB_LSB_ORDER | (1) MSB_LSB_ORDER | 0x0 | Define whether symbol is sent MSB or LSB first
|  | (0) SYMBOL_ORDER | (0) SYMBOL_ORDER | 0x0 | Define whether I sample or Q sample is sent first