# DMA Controller

Address | Register Name | Register Write | Register Read | Default | Description
--- | --- | --- | --- | --- | ---
0x40001200 | DMA0_CFG0 | (31) COMPLETE_INT_ENABLE | (31) COMPLETE_INT_ENABLE | 0x0 | Raise an interrupt when the DMA transfer completes
|  | (30) CNT_INT_ENABLE | (30) CNT_INT_ENABLE | 0x0 | Raise an interrupt when the DMA transfer reaches the counter value
|  | (29) DEST_ADDR_LSB_TOGGLE | (29) DEST_ADDR_LSB_TOGGLE | 0x0 | Enable an address LSB toggling for the destination
|  | (28) SRC_ADDR_LSB_TOGGLE | (28) SRC_ADDR_LSB_TOGGLE | 0x0 | Enable an address LSB toggling for the source
|  | (27:24) DEST_ADDR_STEP | (27:24) DEST_ADDR_STEP | 0x0 | Configure whether the destination address increments/decrements in terms of destination word size
|  | (23:20) SRC_ADDR_STEP | (23:20) SRC_ADDR_STEP | 0x0 | Configure whether the source address increments/decrements in terms of source word size
|  | (19:14) SRC_DEST_WORD_SIZE | (19:14) SRC_DEST_WORD_SIZE | 0x0 | Select the source and destination word sizes for the transfer
|  | (13:10) DEST_SELECT | (13:10) DEST_SELECT | 0x0 | Select the request line for the destination
|  | (8:5) SRC_SELECT | (8:5) SRC_SELECT | 0x0 | Select the request line for the source
|  | (3:2) CHANNEL_PRIORITY | (3:2) CHANNEL_PRIORITY | 0x0 | Select the priority level for this channel
|  | (1) SRC_DEST_TRANS_LENGTH_SEL | (1) SRC_DEST_TRANS_LENGTH_SEL | 0x0 | Selects whether the transfer length counter depends on either the source word counts or the destination word count
|  | (0) BYTE_ORDER | (0) BYTE_ORDER | 0x0 | Select the byte ordering of the DMA channel
0x40001204 | DMA0_CFG1 | (31:16) INT_TRANSFER_LENGTH | (31:16) INT_TRANSFER_LENGTH | 0x0 | Trigger a counter interrupt when the DMA transfer word count reaches this value
|  | (15:0) TRANSFER_LENGTH | (15:0) TRANSFER_LENGTH | 0x0 | The length, in words, of each data transfer using DMA channel
0x40001208 | DMA0_CTRL | (13) INT_CNT_TRIGGER_ENABLE | (13) INT_CNT_TRIGGER_ENABLE | 0x0 | Enable waiting on a trigger when an interrupt counter event occurs
|  | (12:8) TRIGGER_SOURCE | (12:8) TRIGGER_SOURCE | 0x0 | Selects which event triggers this DMA channel when triggering is enabled
|  | (6) INT_CNT_ADDR_WRAP_ENABLE | (6) INT_CNT_ADDR_WRAP_ENABLE | 0x0 | Enable source or destination (depending on SRC_DEST_TRANS_LENGTH_SEL) address wrapping when an interrupt counter event occurs
|  | (5) CLEAR_BUFFER_WHEN_WRAPPING | (5) CLEAR_BUFFER_WHEN_WRAPPING | 0x0 | Clear buffer during address wrapping
|  | (4) BUFFER_CLEAR | - | N/A | Clear source buffer
|  | (3) CNTS_CLEAR | - | N/A | Clear counters
|  | (2:0) MODE_ENABLE | (2:0) MODE_ENABLE | 0x0 | Enable mode of operation of the DMA Channel
0x4000120C | DMA0_STATUS | - | (10) ACTIVE | 0x0 | Active status of the channel
|  | - | (9) CNT_INT | 0x0 | Indicate if a counter interrupt has occurred on DMA channel
|  | - | (8) COMPLETE_INT | 0x0 | Indicate if a complete interrupt has occurred on DMA channel
|  | (6) CNT_INT_CLEAR | - | N/A | Clear the counter interrupt flag
|  | (5) COMPLETE_INT_CLEAR | - | N/A | Clear the complete interrupt flag
|  | (4) SRC_BUFFER_FILL_LVL_WR | - | N/A | Enable writing of SRC_BUFFER_FILL_LVL
|  | (3:0) SRC_BUFFER_FILL_LVL | (3:0) SRC_BUFFER_FILL_LVL | 0x0 | The number of nibbles currently in the source buffer (0: buffer is empty, 8: the 32-bit buffer is completely full)
0x40001210 | DMA0_SRC_ADDR | (31:0) SRC_ADDR | (31:0) SRC_ADDR | 0x0 | Address for the source of data transferred using DMA channel
0x40001214 | DMA0_DEST_ADDR | (31:0) DEST_ADDR | (31:0) DEST_ADDR | 0x0 | Address for the destination of data transferred using DMA channel
0x40001218 | DMA0_CNTS | (31:16) INT_TRANSFER_WORD_CNT | (31:16) INT_TRANSFER_WORD_CNT | 0x0 | Interrupt word counter (automatically reset after each counter interrupt)
|  | (15:0) TRANSFER_WORD_CNT | (15:0) TRANSFER_WORD_CNT | 0x0 | The number of words that have been transferred using DMA channel during the current transfer
0x4000121C | DMA0_SRC_BUFFER | (31:0) SRC_BUFFER | (31:0) SRC_BUFFER | 0x0 | Packed word which has been read from the source addresses.
0x400012FC | DMA0_ID_NUM | - | (20) DMA_24BIT_WORD | 0x0 | 24-bit word size supported
|  | - | (19:16) DMA_NUMBER | 0x0 | DMA channel number
|  | - | (15:8) DMA_MAJOR_REVISION | 0x1 | DMA Major Revision number
|  | - | (7:0) DMA_MINOR_REVISION | 0x0 | DMA Minor Revision number
0x40001300 | DMA1_CFG0 | (31) COMPLETE_INT_ENABLE | (31) COMPLETE_INT_ENABLE | 0x0 | Raise an interrupt when the DMA transfer completes
|  | (30) CNT_INT_ENABLE | (30) CNT_INT_ENABLE | 0x0 | Raise an interrupt when the DMA transfer reaches the counter value
|  | (29) DEST_ADDR_LSB_TOGGLE | (29) DEST_ADDR_LSB_TOGGLE | 0x0 | Enable an address LSB toggling for the destination
|  | (28) SRC_ADDR_LSB_TOGGLE | (28) SRC_ADDR_LSB_TOGGLE | 0x0 | Enable an address LSB toggling for the source
|  | (27:24) DEST_ADDR_STEP | (27:24) DEST_ADDR_STEP | 0x0 | Configure whether the destination address increments/decrements in terms of destination word size
|  | (23:20) SRC_ADDR_STEP | (23:20) SRC_ADDR_STEP | 0x0 | Configure whether the source address increments/decrements in terms of source word size
|  | (19:14) SRC_DEST_WORD_SIZE | (19:14) SRC_DEST_WORD_SIZE | 0x0 | Select the source and destination word sizes for the transfer
|  | (13:10) DEST_SELECT | (13:10) DEST_SELECT | 0x0 | Select the request line for the destination
|  | (8:5) SRC_SELECT | (8:5) SRC_SELECT | 0x0 | Select the request line for the source
|  | (3:2) CHANNEL_PRIORITY | (3:2) CHANNEL_PRIORITY | 0x0 | Select the priority level for this channel
|  | (1) SRC_DEST_TRANS_LENGTH_SEL | (1) SRC_DEST_TRANS_LENGTH_SEL | 0x0 | Selects whether the transfer length counter depends on either the source word counts or the destination word count
|  | (0) BYTE_ORDER | (0) BYTE_ORDER | 0x0 | Select the byte ordering of the DMA channel
0x40001304 | DMA1_CFG1 | (31:16) INT_TRANSFER_LENGTH | (31:16) INT_TRANSFER_LENGTH | 0x0 | Trigger a counter interrupt when the DMA transfer word count reaches this value
|  | (15:0) TRANSFER_LENGTH | (15:0) TRANSFER_LENGTH | 0x0 | The length, in words, of each data transfer using DMA channel
0x40001308 | DMA1_CTRL | (13) INT_CNT_TRIGGER_ENABLE | (13) INT_CNT_TRIGGER_ENABLE | 0x0 | Enable waiting on a trigger when an interrupt counter event occurs
|  | (12:8) TRIGGER_SOURCE | (12:8) TRIGGER_SOURCE | 0x0 | Selects which event triggers this DMA channel when triggering is enabled
|  | (6) INT_CNT_ADDR_WRAP_ENABLE | (6) INT_CNT_ADDR_WRAP_ENABLE | 0x0 | Enable source or destination (depending on SRC_DEST_TRANS_LENGTH_SEL) address wrapping when an interrupt counter event occurs
|  | (5) CLEAR_BUFFER_WHEN_WRAPPING | (5) CLEAR_BUFFER_WHEN_WRAPPING | 0x0 | Clear buffer during address wrapping
|  | (4) BUFFER_CLEAR | - | N/A | Clear source buffer
|  | (3) CNTS_CLEAR | - | N/A | Clear counters
|  | (2:0) MODE_ENABLE | (2:0) MODE_ENABLE | 0x0 | Enable mode of operation of the DMA Channel
0x4000130C | DMA1_STATUS | - | (10) ACTIVE | 0x0 | Active status of the channel
|  | - | (9) CNT_INT | 0x0 | Indicate if a counter interrupt has occurred on DMA channel
|  | - | (8) COMPLETE_INT | 0x0 | Indicate if a complete interrupt has occurred on DMA channel
|  | (6) CNT_INT_CLEAR | - | N/A | Clear the counter interrupt flag
|  | (5) COMPLETE_INT_CLEAR | - | N/A | Clear the complete interrupt flag
|  | (4) SRC_BUFFER_FILL_LVL_WR | - | N/A | Enable writing of SRC_BUFFER_FILL_LVL
|  | (3:0) SRC_BUFFER_FILL_LVL | (3:0) SRC_BUFFER_FILL_LVL | 0x0 | The number of nibbles currently in the source buffer (0: buffer is empty, 8: the 32-bit buffer is completely full)
0x40001310 | DMA1_SRC_ADDR | (31:0) SRC_ADDR | (31:0) SRC_ADDR | 0x0 | Address for the source of data transferred using DMA channel
0x40001314 | DMA1_DEST_ADDR | (31:0) DEST_ADDR | (31:0) DEST_ADDR | 0x0 | Address for the destination of data transferred using DMA channel
0x40001318 | DMA1_CNTS | (31:16) INT_TRANSFER_WORD_CNT | (31:16) INT_TRANSFER_WORD_CNT | 0x0 | Interrupt word counter (automatically reset after each counter interrupt)
|  | (15:0) TRANSFER_WORD_CNT | (15:0) TRANSFER_WORD_CNT | 0x0 | The number of words that have been transferred using DMA channel during the current transfer
0x4000131C | DMA1_SRC_BUFFER | (31:0) SRC_BUFFER | (31:0) SRC_BUFFER | 0x0 | Packed word which has been read from the source addresses.
0x400013FC | DMA1_ID_NUM | - | (20) DMA_24BIT_WORD | 0x0 | 24-bit word size supported
|  | - | (19:16) DMA_NUMBER | 0x0 | DMA channel number
|  | - | (15:8) DMA_MAJOR_REVISION | 0x1 | DMA Major Revision number
|  | - | (7:0) DMA_MINOR_REVISION | 0x0 | DMA Minor Revision number
0x40001400 | DMA2_CFG0 | (31) COMPLETE_INT_ENABLE | (31) COMPLETE_INT_ENABLE | 0x0 | Raise an interrupt when the DMA transfer completes
|  | (30) CNT_INT_ENABLE | (30) CNT_INT_ENABLE | 0x0 | Raise an interrupt when the DMA transfer reaches the counter value
|  | (29) DEST_ADDR_LSB_TOGGLE | (29) DEST_ADDR_LSB_TOGGLE | 0x0 | Enable an address LSB toggling for the destination
|  | (28) SRC_ADDR_LSB_TOGGLE | (28) SRC_ADDR_LSB_TOGGLE | 0x0 | Enable an address LSB toggling for the source
|  | (27:24) DEST_ADDR_STEP | (27:24) DEST_ADDR_STEP | 0x0 | Configure whether the destination address increments/decrements in terms of destination word size
|  | (23:20) SRC_ADDR_STEP | (23:20) SRC_ADDR_STEP | 0x0 | Configure whether the source address increments/decrements in terms of source word size
|  | (19:14) SRC_DEST_WORD_SIZE | (19:14) SRC_DEST_WORD_SIZE | 0x0 | Select the source and destination word sizes for the transfer
|  | (13:10) DEST_SELECT | (13:10) DEST_SELECT | 0x0 | Select the request line for the destination
|  | (8:5) SRC_SELECT | (8:5) SRC_SELECT | 0x0 | Select the request line for the source
|  | (3:2) CHANNEL_PRIORITY | (3:2) CHANNEL_PRIORITY | 0x0 | Select the priority level for this channel
|  | (1) SRC_DEST_TRANS_LENGTH_SEL | (1) SRC_DEST_TRANS_LENGTH_SEL | 0x0 | Selects whether the transfer length counter depends on either the source word counts or the destination word count
|  | (0) BYTE_ORDER | (0) BYTE_ORDER | 0x0 | Select the byte ordering of the DMA channel
0x40001404 | DMA2_CFG1 | (31:16) INT_TRANSFER_LENGTH | (31:16) INT_TRANSFER_LENGTH | 0x0 | Trigger a counter interrupt when the DMA transfer word count reaches this value
|  | (15:0) TRANSFER_LENGTH | (15:0) TRANSFER_LENGTH | 0x0 | The length, in words, of each data transfer using DMA channel
0x40001408 | DMA2_CTRL | (13) INT_CNT_TRIGGER_ENABLE | (13) INT_CNT_TRIGGER_ENABLE | 0x0 | Enable waiting on a trigger when an interrupt counter event occurs
|  | (12:8) TRIGGER_SOURCE | (12:8) TRIGGER_SOURCE | 0x0 | Selects which event triggers this DMA channel when triggering is enabled
|  | (6) INT_CNT_ADDR_WRAP_ENABLE | (6) INT_CNT_ADDR_WRAP_ENABLE | 0x0 | Enable source or destination (depending on SRC_DEST_TRANS_LENGTH_SEL) address wrapping when an interrupt counter event occurs
|  | (5) CLEAR_BUFFER_WHEN_WRAPPING | (5) CLEAR_BUFFER_WHEN_WRAPPING | 0x0 | Clear buffer during address wrapping
|  | (4) BUFFER_CLEAR | - | N/A | Clear source buffer
|  | (3) CNTS_CLEAR | - | N/A | Clear counters
|  | (2:0) MODE_ENABLE | (2:0) MODE_ENABLE | 0x0 | Enable mode of operation of the DMA Channel
0x4000140C | DMA2_STATUS | - | (10) ACTIVE | 0x0 | Active status of the channel
|  | - | (9) CNT_INT | 0x0 | Indicate if a counter interrupt has occurred on DMA channel
|  | - | (8) COMPLETE_INT | 0x0 | Indicate if a complete interrupt has occurred on DMA channel
|  | (6) CNT_INT_CLEAR | - | N/A | Clear the counter interrupt flag
|  | (5) COMPLETE_INT_CLEAR | - | N/A | Clear the complete interrupt flag
|  | (4) SRC_BUFFER_FILL_LVL_WR | - | N/A | Enable writing of SRC_BUFFER_FILL_LVL
|  | (3:0) SRC_BUFFER_FILL_LVL | (3:0) SRC_BUFFER_FILL_LVL | 0x0 | The number of nibbles currently in the source buffer (0: buffer is empty, 8: the 32-bit buffer is completely full)
0x40001410 | DMA2_SRC_ADDR | (31:0) SRC_ADDR | (31:0) SRC_ADDR | 0x0 | Address for the source of data transferred using DMA channel
0x40001414 | DMA2_DEST_ADDR | (31:0) DEST_ADDR | (31:0) DEST_ADDR | 0x0 | Address for the destination of data transferred using DMA channel
0x40001418 | DMA2_CNTS | (31:16) INT_TRANSFER_WORD_CNT | (31:16) INT_TRANSFER_WORD_CNT | 0x0 | Interrupt word counter (automatically reset after each counter interrupt)
|  | (15:0) TRANSFER_WORD_CNT | (15:0) TRANSFER_WORD_CNT | 0x0 | The number of words that have been transferred using DMA channel during the current transfer
0x4000141C | DMA2_SRC_BUFFER | (31:0) SRC_BUFFER | (31:0) SRC_BUFFER | 0x0 | Packed word which has been read from the source addresses.
0x400014FC | DMA2_ID_NUM | - | (20) DMA_24BIT_WORD | 0x0 | 24-bit word size supported
|  | - | (19:16) DMA_NUMBER | 0x0 | DMA channel number
|  | - | (15:8) DMA_MAJOR_REVISION | 0x1 | DMA Major Revision number
|  | - | (7:0) DMA_MINOR_REVISION | 0x0 | DMA Minor Revision number
0x40001500 | DMA3_CFG0 | (31) COMPLETE_INT_ENABLE | (31) COMPLETE_INT_ENABLE | 0x0 | Raise an interrupt when the DMA transfer completes
|  | (30) CNT_INT_ENABLE | (30) CNT_INT_ENABLE | 0x0 | Raise an interrupt when the DMA transfer reaches the counter value
|  | (29) DEST_ADDR_LSB_TOGGLE | (29) DEST_ADDR_LSB_TOGGLE | 0x0 | Enable an address LSB toggling for the destination
|  | (28) SRC_ADDR_LSB_TOGGLE | (28) SRC_ADDR_LSB_TOGGLE | 0x0 | Enable an address LSB toggling for the source
|  | (27:24) DEST_ADDR_STEP | (27:24) DEST_ADDR_STEP | 0x0 | Configure whether the destination address increments/decrements in terms of destination word size
|  | (23:20) SRC_ADDR_STEP | (23:20) SRC_ADDR_STEP | 0x0 | Configure whether the source address increments/decrements in terms of source word size
|  | (19:14) SRC_DEST_WORD_SIZE | (19:14) SRC_DEST_WORD_SIZE | 0x0 | Select the source and destination word sizes for the transfer
|  | (13:10) DEST_SELECT | (13:10) DEST_SELECT | 0x0 | Select the request line for the destination
|  | (8:5) SRC_SELECT | (8:5) SRC_SELECT | 0x0 | Select the request line for the source
|  | (3:2) CHANNEL_PRIORITY | (3:2) CHANNEL_PRIORITY | 0x0 | Select the priority level for this channel
|  | (1) SRC_DEST_TRANS_LENGTH_SEL | (1) SRC_DEST_TRANS_LENGTH_SEL | 0x0 | Selects whether the transfer length counter depends on either the source word counts or the destination word count
|  | (0) BYTE_ORDER | (0) BYTE_ORDER | 0x0 | Select the byte ordering of the DMA channel
0x40001504 | DMA3_CFG1 | (31:16) INT_TRANSFER_LENGTH | (31:16) INT_TRANSFER_LENGTH | 0x0 | Trigger a counter interrupt when the DMA transfer word count reaches this value
|  | (15:0) TRANSFER_LENGTH | (15:0) TRANSFER_LENGTH | 0x0 | The length, in words, of each data transfer using DMA channel
0x40001508 | DMA3_CTRL | (13) INT_CNT_TRIGGER_ENABLE | (13) INT_CNT_TRIGGER_ENABLE | 0x0 | Enable waiting on a trigger when an interrupt counter event occurs
|  | (12:8) TRIGGER_SOURCE | (12:8) TRIGGER_SOURCE | 0x0 | Selects which event triggers this DMA channel when triggering is enabled
|  | (6) INT_CNT_ADDR_WRAP_ENABLE | (6) INT_CNT_ADDR_WRAP_ENABLE | 0x0 | Enable source or destination (depending on SRC_DEST_TRANS_LENGTH_SEL) address wrapping when an interrupt counter event occurs
|  | (5) CLEAR_BUFFER_WHEN_WRAPPING | (5) CLEAR_BUFFER_WHEN_WRAPPING | 0x0 | Clear buffer during address wrapping
|  | (4) BUFFER_CLEAR | - | N/A | Clear source buffer
|  | (3) CNTS_CLEAR | - | N/A | Clear counters
|  | (2:0) MODE_ENABLE | (2:0) MODE_ENABLE | 0x0 | Enable mode of operation of the DMA Channel
0x4000150C | DMA3_STATUS | - | (10) ACTIVE | 0x0 | Active status of the channel
|  | - | (9) CNT_INT | 0x0 | Indicate if a counter interrupt has occurred on DMA channel
|  | - | (8) COMPLETE_INT | 0x0 | Indicate if a complete interrupt has occurred on DMA channel
|  | (6) CNT_INT_CLEAR | - | N/A | Clear the counter interrupt flag
|  | (5) COMPLETE_INT_CLEAR | - | N/A | Clear the complete interrupt flag
|  | (4) SRC_BUFFER_FILL_LVL_WR | - | N/A | Enable writing of SRC_BUFFER_FILL_LVL
|  | (3:0) SRC_BUFFER_FILL_LVL | (3:0) SRC_BUFFER_FILL_LVL | 0x0 | The number of nibbles currently in the source buffer (0: buffer is empty, 8: the 32-bit buffer is completely full)
0x40001510 | DMA3_SRC_ADDR | (31:0) SRC_ADDR | (31:0) SRC_ADDR | 0x0 | Address for the source of data transferred using DMA channel
0x40001514 | DMA3_DEST_ADDR | (31:0) DEST_ADDR | (31:0) DEST_ADDR | 0x0 | Address for the destination of data transferred using DMA channel
0x40001518 | DMA3_CNTS | (31:16) INT_TRANSFER_WORD_CNT | (31:16) INT_TRANSFER_WORD_CNT | 0x0 | Interrupt word counter (automatically reset after each counter interrupt)
|  | (15:0) TRANSFER_WORD_CNT | (15:0) TRANSFER_WORD_CNT | 0x0 | The number of words that have been transferred using DMA channel during the current transfer
0x4000151C | DMA3_SRC_BUFFER | (31:0) SRC_BUFFER | (31:0) SRC_BUFFER | 0x0 | Packed word which has been read from the source addresses.
0x400015FC | DMA3_ID_NUM | - | (20) DMA_24BIT_WORD | 0x0 | 24-bit word size supported
|  | - | (19:16) DMA_NUMBER | 0x0 | DMA channel number
|  | - | (15:8) DMA_MAJOR_REVISION | 0x1 | DMA Major Revision number
|  | - | (7:0) DMA_MINOR_REVISION | 0x0 | DMA Minor Revision number