# PWM

The RSL15 system contains five pulse-width modulator (PWM) drivers, which can be configured to generate a single output signal with a specified period and duty cycle. Each PWM driver can be used independently as a simple D/A converter.

The PWM drivers are multiplexed onto the GPIO pads, which can be configured as output signals with the necessary physical pad configuration (GPIO_MODE_PWM*). The GPIOs support output of the PWM signals with the specified period and high-time in each period and the inverse of the specified signal (GPIO_MODE_PWM*_INV). For more information about configuring the multiplexed GPIO functionality, see General Purpose Input/Output.

The timing and shape of the signal produced by each PWM is defined by clock signals that are divided from SYSCLK or SLOWCLK, and by the PWM_PERIOD* register and PWM_HIGH* register.

The PWM drivers are supported by a clock (PWM*CLK) that is sourced from SLOWCLK or SYSCLK using the CLK_DIV_CFG2_PWM_CLK_SRC bit field from the CLK_DIV_CFG2 register.

The value written to the PWM_CFG_PWM_PERIOD bit field configures the number of PWM*CLK cycles in one period of that PWM signal. Each period is () PWM*CLK cycles in length, with a maximum length of 4096 PWM*CLK cycles.

Similarly, the value written to the PWM_CFG_PWM_HIGH bit field configures the number of PWM*CLK cycles for which the PWM signal is high in each period. The PWM signal is high for the first
() PWM*CLK cycles of each period, to a maximum equal to the period of that PWM signal. After () PWM*CLK cycles, the PWM signal is low for the remainder of the period.

NOTE: If the specified high time is greater than or equal to the specified period for a PWM, the PWM signal does not go low.

PWM Sample Configuration (figure) illustrates an example PWM configuration for PWM0, where the PWM period is configured for 10 cycles (PWM_CFG_PWM_PERIOD set to 9), with a high time of 6 cycles (PWM_CFG_PWM_HIGH set to 5). This results in a PWM signal that repeats every 10 PWM0CLK cycles, with a duty cycle of 60%.

Figure: PWM Sample Configuration

Each PWM driver can be independently enabled and disabled by configuring the PWM_CTRL_PWM*_ENABLE bit field from the PWM_CTRL register.

The PWM drivers also support dithering. Each PWM channel has 8‑bit dithering based on the van der Corput sequence. To configure dithering, the PWM_HIGH register’s PWM_HIGH*_HIGH_FRACTIONAL bitfield of the corresponding driver must be set to a value higher than 1, to a maximum of 255.

NOTE: PWM channel 0 must be active to have dithering on any PWM channel.

When dithering is active, the PWM driver adds or subtracts a single clock cycle over a PWM_PERIOD, where the total amount of cycles added over 256 periods is equal to the value set in the PWM_HIGH*_HIGH_FRACTIONAL bitfield in the PWM_HIGH register.

If a PWM driver uses the same period and clock divisor as PWM0, the relative timing between the PWM driver and PWM0 can be defined. To enable offset configuration, set the PWM_OFFSET*_OFFSET_ENABLE bit from the PWM_OFFSET* register. When this configuration is enabled, the number of cycles between the rising edge for PWM0 and the rising edge for the configured PWM* is equal to the value of the PWM_OFFSET*_OFFSET bit field from the PWM_OFFSET* register.

NOTE: If the specified offset is greater than or equal to the specified period for the PWM drivers, the behavior is undefined. The behavior is similarly undefined if PWM* does not share its period and clock divisor configuration with PWM0.

## ACS_PWM

The ACS-PWM block is another PWM driver that can output a signal during low power modes when most of the device is powered down. This is possible because ACS-PWM is part of the Analog Control Sub System (ACS), which is always on. The ACS-PWM is mapped to GPIO4 and cannot be changed. Before enabling the ACS-PWM, GPIO4 must be set to GPIO_MODE_DISABLE and GPIO_NO_PULL.

The ACS-PWM clock is sourced from the 32,768 Hz RTCCLK.

The ACS-PWM is enabled via the ACS_PWM_AO_CTRL_PWM_ENABLE bit in the ACS_PWM_AO_CTRL register. This register is also used to disable the module and reset the counter via the ACS_PWM_AO_CTRL_PWM_DISABLE and ACS_PWM_AO_CTRL_PWM_RESET bits appropriately.

The ACS-PWM block functions similarly to the standard PWM module, except that the ACS-PWM’s period and high states are limited to a range of 1 to 256, instead of 1 to 4096, due to the 8-bit size of the ACS_PWM_AO_CFG_PERIOD bit field and ACS_PWM_AO_CFG_HIGH bit field in the ACS_PWM_AO_CFG register. For information on how the PERIOD and HIGH bit fields configure the PWM waveform, see PWM.

For registers, see PWM Registers.