# Clock Generation

## RC Oscillator

The RC oscillator is a ring oscillator that produces a trimmable output clock (RCCLK), which is used by the RSL15 system as SYSCLK at startup. It can be used while operating in Run Mode without RF traffic, to minimize current consumption and to maximize the amount of processing that can be completed while waiting for the 48 MHz oscillator when it is started. Enable the RC oscillator by setting the ACS_RCOSC_CTRL_RC_OSC_EN bit from the ACS_RCOSC_CTRL register.

The RC oscillator is configured using the ASC_RCOSC_CTRL register, including:

- A coarse trimming that selects nominal untrimmed settings between 3 and 48 MHz using the ASC_RCOSC_CTRL_RC_FSEL bit field (defaulting to 3 MHz)
- A fine trimming using the ACS_RCOSC_CTRL_RC_FTRIM bit-field
- If you have used a calibrated value, set the ACS_RCOSC_CTRL_RC_FTRIM_FLAG status flag indicating that a device has been trimmed with a calibrated value.
- The trimming range for this oscillator can be shifted down by approximately 15% by setting the ACS_RCOSC_CTRL_RC_FTRIM_ADJ bit.

Calibrated values for trim settings are provided as part of the manufacturing records in MNVR. For more information, see the RSL15 Firmware Reference.

RCCLK can be output through one or more GPIO pads using the GPIO components. For more information about the GPIO configuration, see Functional Configuration.

IMPORTANT: The RC oscillator supports trimming at up to 24 MHz for all system conditions. For system configurations that ensure VCC ≥ 1.2 V, the RC oscillator supports trimming up to 48 MHz.

## 48 MHz Crystal Oscillator

The RF front-end for the RSL15 system includes a 48 MHz crystal oscillator. To use this crystal oscillator, the RF front-end must be powered with access enabled, as described in Overview.

To enable the 48 MHz crystal oscillator, set the XTAL_CTRL_XO_EN_B_REG bit from the RF front-end XTAL_CTRL register. When enabled, the 48 MHz crystal oscillator takes some time before it is ready for the rest of the system to use. When this clock is ready, the ANALOG_INFO_CLK_DIG_READY bit from the ANALOG_INFO RF front-end register is set. When the PLL based on this oscillator is ready, the ANALOG_INFO_CLK_PLL_READY bit from the ANALOG_INFO RF front-end register is also set. Information about further configuration of this oscillator can be found in RFFE System Resources.

NOTE: When processing RF traffic, the RF front-end is always directly clocked from the 48 MHz crystal oscillator, with the analog components of the RF front-end using a frequency synthesizer to produce an appropriate carrier for the RF traffic in the 2.4 GHz RF band.

The 48 MHz crystal oscillator is divided using the 3-bit prescaler, defined in the RF_REG33_CK_DIV_1_6_CK_DIV_1_6 bit-field from the RF_REG33 RF front-end register, to produce RFCLK. This clock, which divides the 48 MHz clock source by a factor between 1 and 7, can be used as the source for SYSCLK, or output through one or more GPIO pads using the GPIO components. For more information about the GPIO configuration, see Functional Configuration.

The 48 MHz crystal oscillator is trimmed using the XTAL_TRIM_XTAL_TRIM_INIT and XTAL_TRIM_XTAL_TRIM bit-fields from the XTAL_TRIM register. When the underlying 48 MHz crystal is specified for the default load capacitance of 8 pF, both of these bit-fields must be set to their defaults (0x60). If a 48 MHz crystal with a different load capacitance is selected, then the crystal must be trimmed by following these steps:

1. Configure and enable the RFCLK, configuring the RF_REG33_CK_DIV_1_6_CK_DIV_1_6 bit-field to prescale the 48 MHz oscillator by a factor of 6 (RFCLK will be 8 MHz).
2. Set up a GPIO to output RFCLK. (For more information about configuring GPIOs, see General Purpose Input/Output.)
3. Set both XTAL_TRIM_XTAL_TRIM_INIT and XTAL_TRIM_XTAL_TRIM bit-fields to their default trim of 0x60.
4. Measure RFCLK output on the selected GPIO, adjusting XTAL_TRIM_XTAL_TRIM until the output RFCLK is as close to 8 MHz as possible.
5. Repeat this measurement over a population of 48 MHz crystals, having set both the XTAL_TRIM_XTAL_TRIM_INIT and XTAL_TRIM_XTAL_TRIM bit-fields to the trimmed value, to ensure that the expected distribution on the XTAL's initial frequency tolerance remains sufficiently well centered across the population.

NOTE: The accuracy of the selected trim can be validated using Bluetooth Low Energy test case TP/TRM-LE/CA/BV-06-C [Carrier frequency offset and drift at 1 Ms/s]. For this test, the frequency accuracy is expected to be well centered around 0 kHz, and not near the test limits of ±150 kHz.

## Standby RC Oscillator

The standby RC oscillator is a ring oscillator that produces a trimmable output clock, which can be used by the RSL15 system as a source for STANDBYCLK, and hence as a source for the RTC. This oscillator produces a nominal output frequency of 32 kHz. Enable the standby RC oscillator by setting the ACS_RCOSC_CTRL_RC32_OSC_EN bit from the ACS_RCOSC_CTRL register.

The frequency of the standby RC oscillator is trimmed using the ACS_RCOSC_CTRL_RC32_FTRIM bit-field from the ACS_RCOSC_CTRL register. The trimming range for this oscillator can be shifted down by approximately 25% (producing a clock with a nominal output frequency of 24 kHz) by setting the ACS_RCOSC_CTRL_RC32_FTRIM_ADJ bit from the ACS_RCOSC_CTRL register.

IMPORTANT: If the standby RC oscillator is used as a source of timing for RF traffic, this oscillator needs to be measured using the 48 MHz crystal oscillator and the asynchronous clock counter. Make appropriate adjustments to the Bluetooth baseband timer driven counters and RTC starting countdown setting stored to the ACS_RTC_CFG_START_VALUE bit-field from the ACS_RTC_CFG register.

For more information about configuring the RTC, see Real Time Clock (RTC). For more information about measuring the standby RC oscillator using the asynchronous clock counter, see Asynchronous Clock Counter.

## 32 kHz Crystal Oscillator

The 32 kHz crystal oscillator provides a very low-power, accurate reference clock that can be used as the source for the baseband and RTC when timing RF traffic and other elements where a high-accuracy clock is required. The 32 kHz crystal oscillator is a Pierce oscillator that provides a 32768 Hz reference clock. Configure it by using the ACS_XTAL32K_CTRL register. Configuration and status options for this oscillator include the following:

- The oscillator can be enabled or disabled by configuring the ACS_XTAL32K_CTRL_ENABLE bit.
- The ACS_XTAL32K_CTRL_READY bit indicates when the oscillator output is available for use. This status can be forced using the ACS_XTAL32K_CTRL_FORCE_ENABLE bit; however, using this option is not recommended.
- The trim parameters for interacting with the external 32 kHz crystals can be trimmed to do the following:
  - Provide a variety of different startup current levels using the ACS_XTAL32K_CTRL_ITRIM bit-field (which sets the nominal startup current levels) and the ACS_XTAL32K_CTRL_IBOOST bit (which boosts the startup currents by an approximate factor of 4)
  - Provide an appropriate capacitive load, configured using the ACS_XTAL32K_CTRL_CLOAD_TRIM bit-field
- The output from the crystal can be configured to do the following:
  - Enable or disable regulation of the amplitude of the crystal output using the ACS_XTAL32K_CTRL_EN_AMPL_CTRL bit
  - Include or bypass the serial output cap for the oscillator, configured using the ACS_XTAL32K_CTRL_XIN_CAP_BYPASS_EN bit. If the external crystal selected does not need this buffering capacitor, removing this capacitor can reduce the leakage of the 32 kHz crystal oscillator.

If the crystal oscillator temporarily fails and is not okay at any point after becoming ready, the ACS_XTAL32K_CTRL_XTAL_N_OK status bit is set in the ACS_XTAL32K_CTRL register. This sticky status bit is only cleared when the ACS_XTAL32K_CTRL_XTAL_N_OK_RESET bit is set.

IMPORTANT: There is a notable startup time for the 32 kHz crystal oscillator once it is activated. When this oscillator is ready for use, the ACS_XTAL32K_CTRL_READY bit is set in the ACS_XTAL32K_CTRL register. The startup time for the crystal increases exponentially with increased capacitance, as controlled by using the ACS_XTAL32K_CTRL_CLOAD_TRIM bit-field from the ACS_XTAL32K_CTRL register. For example, with this bit-field configured for a load of 23.2 pF, the startup time is approximately two seconds. Enabling the ACS_XTAL32K_CTRL_FORCE_READY flag bypasses the crystal oscillator ready circuitry. However, this does not greatly improve the startup time, since the main time contributor is the crystal oscillator's required startup time. Boosting the startup time by bypassing the crystal ready circuit is not a safe approach, and is not recommended. If accurate timing is required, we recommend waiting for the ACS_XTAL32K_CTRL_READY flag to be set before using the 32 kHz crystal oscillator, as the clock could be unstable or missing for some period of time prior to this flag being set. While waiting for the 32 kHz crystal oscillator to be ready, other system tasks that do not require this oscillator can be completed in all conditions. ACS_XTAL32K_CTRL_CLOAD_TRIM must match the crystal component CLOAD. The crystal frequency's accuracy is impacted by the parasitic capacitances outside of the chip, and also by the specifications of the chosen external resonator. For any new application, and in a case where the type of resonator is changed, we recommend performing the following calibration: Output the crystal clock frequency on a GPIO to measure the frequency using default trimmings. Adjust ACS_XTAL32K_CTRL_CLOAD_TRIM to have an exact frequency of 32768 kHz. The trimming steps are only a few ppms. Ideally, ACS_XTAL32K_CTRL_CLOAD_TRIM is intended to be twice the value specified by the resonator provider. But the parasitic capacitance of the board requires using a smaller value. Once the ACS_XTAL32K_CTRL_CLOAD_TRIM is defined for the application, the startup current (controlled by ACS_XTAL32K_CTRL_ITRIM and ACS_XTAL32K_CTRL_IBOOST) needs to be calibrated. Do this by measuring the startup time of the crystal for all startup current configurations and select the configuration that gives the desirable startup time. ATTENTION: The 32 KHz crystal oscillator can fail to start if CLOAD is not properly tuned to achieve the correct center frequency.

## Debug Port Clock

The JTCK signal from the SWJ-DP interface in the RSL15 system can be used as an external input clock source that supplies SYSCLK. Prior to use in clocking the system, this clock is prescaled using the CLK_SYS_CFG_JTCK_PRESCALE bit-field from the CLK_SYS_CFG register. This produces a divided JTCK clock output that is prescaled by between 1 and 16 to produce a potential SYSCLK frequency defined by:

IMPORTANT: Only use the JTCK pad as an input clock source if the SWJ-DP interface is configured for JTAG mode or is not used. For more information about debug port configuration, see Debug Port.