# Ultra-Low Power Data Acquisition Subsystem

The ultra-low power (ULP) data acquisition subsystem collects data from the SAR-ADC (see SAR-ADC ) and pulse counter (see Pulse Counter), optionally routing this data through an accumulator, and distributing the data through a FIFO and threshold detection circuitry for further processing in the rest of the RSL15 system.

An overview of the ULP data acquisition subsystem is provided in the "Top-Level Overview of the Data Acquisition Subsystem" figure.

Figure: Top-Level Overview of the Data Acquisition Subsystem

The ULP data acquisition subsystem is designed to be used in any power mode, and can be used to trigger a transition between Run Mode and one of the following:

- A low power mode (such as Standby Mode)
- Smart Sense Mode

For more information on power modes, see Power Modes.

The ULP data acquisition subsystem is controlled by the SENSOR_CTRL register:

- Reset the ULP data acquisition subsystem, including the SAR-ADC, by setting the SENSOR_CTRL_RESET bit

- The subsystem can be enabled or disabled using the SENSOR_CTRL_ENABLE bit.

  - If the ULP data acquisition subsystem is currently sampling from the SAR-ADC when disabled, the sample conversion is completed before the system transitions to an idle state.

IMPORTANT: If the ULP data acquisition subsystem is reset while using the SAR-ADC (whether used with the ULP data acquisition subsystem or separately), the SAR-ADC must be re-calibrated.

The state of the ULP data acquisition subsystem is also available in the SENSOR_CTRL register:

- The SENSOR_CTRL_STATUS bit indicates if the ULP data acquisition subsystem is idle or active. Since the ULP data acquisition subsystem might not be disabled immediately when the SENSOR_CTRL_ENABLE bit is cleared, this status bit is used to indicate when the subsystem actually becomes idle.

- The SENSOR_CTRL_STATE bit indicates if the ULP data acquisition subsystem is currently sampling data using the pulse counter or SAR-ADC, or if it is in an idle/delay state.

## Clock Source Configuration

The ULP data acquisition subsystem is clocked using SENSOR_CLK or STANDBYCLK, as selected via the SENSOR_CFG_CLK_SEL bit from the SENSOR_CFG register. If SENSOR_CLK is selected as the clock source, the ULP data acquisition subsystem disables SENSOR_CLK when switching to sleep or standby power modes. For more information on power modes, see Power Modes.

IMPORTANT: The ULP data acquisition subsystem must be disabled when switching between clock sources, as SENSOR_CLK and STANDBYCLK are not synchronous and the resulting clock switch cannot otherwise be guaranteed to be glitch free.

SENSOR_CLK is divided from SYSCLK using the CLK_CFG1_SENSOR_CLK_PRESCALE bit-field from the CLK_CFG1 register. If not used, SENSOR_CLK can be disabled using the CLK_CFG1_SENSOR_CLK_DISABLE bit from the CLK_CFG1 register.

## Input Configuration

The input to the ULP data acquisition subsystem is controlled by the SENSOR_CFG_SRC_SEL bit from the SENSOR_CFG register, selecting between sourcing data from the SAR-ADC (see SAR-ADC ) and the pulse counter (see Pulse Counter).

NOTE: While the pulse counter is used as the input to the ULP data acquisition subsystem, the SAR-ADC input can continue to be used in parallel using the SENSOR_SAR_DATA register or the DMA block (see DMA Controller) to obtain data from the SAR-ADC.

The time between retrieving input data samples (and the delay before reading the first sample) from the SAR-ADC can be configured using the SENSOR_CFG register:

- Enable the sampling delay by setting the SENSOR_CFG_DLY_EN bit.

- Configure the sampling delay, as a multiple of the selected clock source of between 1 and 1024 cycles, using the SENSOR_CFG_DLY_DIV_EN bit-field.

NOTE: Sampling delays for the SAR-ADC do not apply when accessing SAR-ADC data using the SENSOR_SAR_DATA register or the DMA block.

## Sample Accumulation

The input samples can be accumulated before being stored and post-processed. When the accumulator is enabled, samples output from the accumulation block is used by the sample storage and signal threshold detection blocks in place of using the input samples directly.

The accumulator sums the number of samples specified by the SAMPLE_PROCESSING_NBR_SAMPLES bit-field, from the SAMPLE_PROCESSING register whenever it is enabled using the SAMPLE_PROCESSING_SUM_EN bit from the same register. The summation time duration is equivalent to the duration of one sample, multiplied by the number of samples selected in the SAMPLE_PROCESSING_NBR_SAMPLES bit-field. The accumulator can be used to accumulate (n – 1) samples at a time, with the last sample in a set of n samples needing to be manually read from SENSOR_SAR_DATA and added to the accumulated result when an event occurs. If the accumulator is used with the ULP sensor’s FIFO, every n th sample is ignored, because the last sample in each set is not manually accumulated when using the FIFO or threshold detector.

IMPORTANT: The SAMPLE_PROCESSING_NBR_SAMPLES bit-field from the SAMPLE_PROCESSING register is shared with the threshold detection block. If both sample accumulation and threshold detection are enabled, they use the same value for this bit field.

## Sample Storage

The samples collected by the ULP data acquisition subsystem can be stored to a FIFO dedicated to the subsystem. The FIFO is based around a 16-entry buffer stored to the SENSOR_FIFO_DATA* registers. The FIFO configuration and status of the FIFO buffer is provided by the SENSOR_FIFO_CFG register:

- To enable sample storage in the FIFO, set the SENSOR_FIFO_CFG_FIFO_STORE_EN bit.

- To set the size of the FIFO used, configure the SENSOR_FIFO_CFG_FIFO_SIZE bit-field.

- To query the current FIFO level, read the SENSOR_FIFO_CFG_FIFO_LEVEL bit-field.

The FIFO supports triggering three different events when it becomes full, as indicated by the FIFO level being equal to or greater than the defined FIFO size. When the FIFO becomes full, the following events are triggered if their conditions are met:

- A FIFO interrupt is triggered when the ULP data acquisition subsystem is clocked using SENSOR_CLK, and the SENSOR_FIFO_CFG_FIFO_RX_INT_EN bit is set.

- A wakeup event and WAKEUP interrupt is triggered, indicating the wakeup has been triggered by the FIFO_FULL wakeup source, when the ULP data acquisition subsystem is clocked using STANDBYCLK. This includes ULP data acquisition subsystem operation in all power modes other than run mode. For more information about power modes, see Power Modes.

- A DMA trigger is sent to start one or more DMA channel operations when the SENSOR_FIFO_CFG_FIFO_RX_DMA_EN bit is set. For more information about DMA triggers and DMA channel operations, see Direct Memory Access (DMA) Controller.

IMPORTANT: The FIFO level provided by the SENSOR_FIFO_CFG_FIFO_LEVEL bit-field is updated asynchronously to the rest of the system, when the ULP data acquisition subsystem is clocked using STANDBYCLK. If the FIFO level is not pointing to the last entry in the FIFO buffer, this value needs to be read until the same value is read twice consecutively, to confirm the actual level of the FIFO has been read cleanly.

NOTE: The FIFO does not reset when there is a digital reset, and the FIFO buffer contains undefined data at system start up. The SENSOR_FIFO_CFG_FIFO_LEVEL bit-field indicates which data in the FIFO is valid.

The FIFO level is reset when the first entry in the FIFO buffer is read. When reading the first sample in the FIFO, all other valid data needs to be read as well — before it is overwritten with new samples. Practically, this means that the second and subsequent samples must be read no more than one sampling period of the SAR-ADC or pulse counter (including delays and accumulation) after reading of the previous sample.

The FIFO does not provide any error handling for edge cases:

- The FIFO does not support overflow detection. If additional samples are received when the FIFO is full, new samples continue to be written to the FIFO buffer with the FIFO level saturated at the last entry in the 16-entry buffer, which is overwritten repeatedly until the first value for the FIFO is read and the FIFO level is reset.

- The FIFO does not support underflow detection. Data read from the FIFO buffer past the FIFO level read from the SENSOR_FIFO_CFG_FIFO_LEVEL bit-field prior to reading the first sample in the buffer, is undefined.

- The FIFO does not support protection of received samples after the first entry in the FIFO buffer (the first sample is protected by not allowing overflow of the FIFO buffer).

## Signal Threshold Detection

The ULP data acquisition subsystem contains a threshold detection block that can be used alongside the sample storage block. The threshold block is used to compare the values created by the rest of the ULP data acquisition subsystem to determine if a number of consecutive received samples are:

- Above or equal to the maximum threshold detection level

- Below or equal to the minimum threshold detection level

- Outside of the range defined by the minimum and maximum threshold detection levels

Threshold detection is enabled whenever one or both thresholds are enabled:

- The maximum threshold is configured using the SENSOR_THRESHOLD_MAX register. The level for the maximum threshold is set by the SENSOR_THRESHOLD_MAX_THRESHOLD_MAX bit-field, and this threshold is enabled using the SENSOR_THRESHOLD_MAX_THRESHOLD_MAX_EN bit.

- The minimum threshold is configured using the SENSOR_THRESHOLD_MIN register. The level for the minimum threshold is set by the SENSOR_THRESHOLD_MIN_THRESHOLD_MIN bit-field, and this threshold is enabled using the SENSOR_THRESHOLD_MIN_THRESHOLD_MIN_EN bit.

The number of consecutive samples that need to meet a threshold condition before a wakeup event occurs is configured using the SAMPLE_PROCESSING_NBR_SAMPLES bit-field from the SAMPLE_PROCESSING register.

IMPORTANT: The SAMPLE_PROCESSING_NBR_SAMPLES bit-field from the SAMPLE_PROCESSING register is shared with the sample accumulation block. If both sample accumulation and threshold detection are enabled, they use the same value for this bit field.

The threshold block is used to trigger a wakeup event and WAKEUP interrupt, indicating the wakeup has been triggered by the THRESHOLD wakeup source. This event is triggered when one or both of the enabled threshold conditions is met over the specified number of consecutive samples.

For registers, see ULP Registers.