# Direct Control

RSL15 can configure any of the general-purpose input/output (GPIO) pads directly, rather than using them through an interface. The function of these GPIO pads is defined by a user application, which can use them for any general-purpose input or output.

The GPIO_MODE register indicates which GPIO pads have been configured for direct application control of the GPIO functionality; bits in this register are set (for example, GPIO*_IS_GPIO_MODE) if they are configured as GPIOs, and cleared otherwise (for example, GPIO_IS_NOT_GPIO_MODE). For any pads that are defined as being in a direct control GPIO mode, the GPIO_DIR register can be written to set the input/output direction for these pads, or read to query the direction of the pads.

The value observed at the digital input pads can be read from the GPIO_INPUT_DATA register. This value is read as 0 for all pads configured as LSAD inputs (see LSAD), because the digital input is not enabled in this mode. For all other modes, the physical value of the pad is directly measured. The output value driven to the digital output pads can also be set or queried using the GPIO_OUTPUT_DATA register for any pads that are configured as application-controlled GPIO outputs. Additionally, GPIO outputs can be set or cleared using the GPIO_OUTPUT_DATA_SET and GPIO_OUTPUT_DATA_CLR registers, without changing any other GPIO output values.

IMPORTANT: If any GPIOs are unprotected in Trustzone non-secure code (that is, NS_CAN_USE_GPIO has been used to set the GPIO_CFG_NS_ACCESS_GPIO bit in any GPIO_CFG register), use of the GPIO_OUTPUT_DATA_CLR, GPIO_OUTPUT_DATA_SET and GPIO_DIR registers is not supported. In this configuration, all GPIO direction configuration must use the GPIO_CFG registers and all direct access to GPIO output data must use the GPIO_OUTPUT_DATA register.

## GPIO Interrupts

The GPIOs are supported by a set of four general-purpose configurable interrupts which, when enabled, signal the occurrence of an event or a condition on a specified GPIO pad. See Nested Vector Interrupt Controller (NVIC) for information regarding interrupt configuration and handling.

Each of the GPIO interrupts can use any of the 16 GPIOs as the triggering input source for the interrupt. Each of the GPIO interrupts also supports triggering on one of five possible GPIO events. The source and event trigger for each interrupt can be configured using one of the bit fields in the GPIO_INT_CFG registers. For each of the four interrupts:

- To select the GPIO pad to use as a trigger for the interrupt, set the GPIO_INT_CFG_SRC bit field.
- To select the event to use as a trigger for the interrupt, use the GPIO_INT_CFG_EVENT bit field. A list of the possible triggering events (including a description of each event) is listed in the "GPIO Interrupt Triggering Events" table.

Table: GPIO Interrupt Triggering Events
Event | Event Description
--- | ---
Disabled | An interrupt is never generated.
High level | An interrupt is generated whenever a logical 1 is detected on the GPIO pin. Interrupts continue to be generated while this condition remains true.
Low level | An interrupt is generated whenever a logical 0 is detected on the GPIO pin. Interrupts continue to be generated while this condition remains true.
Rising edge | An interrupt is generated when a transition from a logical 0 to a logical 1 is detected.
Falling edge | An interrupt is generated when a transition from a logical 1 to a logical 0 is detected.
Transition | An interrupt is generated when any transition between a logical 0 and a logical 1 is detected.

Each of the GPIO interrupts can be configured to use a debounce filter to eliminate extraneous interrupt triggers; to enable the debounce filter, set the GPIO_INT_CFG_DEBOUNCE_ENABLE bits from the GPIO_INT_CFG registers. If enabled, the debounce filters:

| • | Transition their output to the new value for the GPIO as soon as detected.

| • | Hold this new output value for a period of time as defined by the GPIO_INT_DEBOUNCE register; its GPIO_INT_DEBOUNCE_DEBOUNCE_CLK bit selects the SLOWCLK divider used for the debounce clock (selecting between 32 and 1024 cycles), and the GPIO_INT_DEBOUNCE_DEBOUNCE_COUNT bit-field, also in the GPIO_INT_DEBOUNCE register, sets the number of these divided clock cycles to use for the hold period.

| • | After the hold period has expired, the debounce filter transitions the filters' output to the input value and begins monitoring for new transitions.

| • | The hold time is reset if the debounce filter configuration is changed, the GPIO interrupt source configuration is changed, or the GPIO interrupt is disabled.

Each GPIO interrupt can also be configured to be accessible or inaccessible in non-secure execution modes using the GPIO_INT_CFG_NS_ACCESS bit in the appropriate GPIO_INT_CFG register. For more information about non-secure application execution, see Arm TrustZone CryptoCell-312 Security IP.