# Asynchronous Clock Counter

The asynchronous clock counter (ASCC) can be used to measure the timing of a clock through the internal STANDBYCLK, or the timing of a clock in a connected external device. In addition, the ASCC can be used to measure the frequency of the internal 32 kHz RC oscillator using the 48 MHz crystal oscillator.

The following ASCC uses are supported:

- Generation of control information to synchronize the RSL15 system's sampling frequency with the signal of an external connected device
- Measurement of the internal STANDBYCLK oscillator relative to the SYSCLK frequency through a GPIO pad
- Measurement of the internal 32 kHz RC oscillator

IMPORTANT: The asynchronous clock being measured is sourced from a GPIO or from STANDBYCLK, as specified by the GPIO configuration. For more information on GPIO configuration for use as the asynchronous clock source, see Functional Configuration.

The timing diagram in the "Asynchronous Clock Counters Timing Diagram" figure highlights the measurement registers in the Asynchronous Clock module.

Figure: Asynchronous Clock Counters Timing Diagram

The measurement registers are defined as follows:

- The ASCC_CNT register holds the integer number of cycles of the asynchronous clock (saturated to 0x0FFF) being measured between consecutive synchronization pulses.
- The ASCC_PERIOD_CNT register contains the period count of the asynchronous clock (saturated to 0x0FFF) being measured in terms of SYSCLK cycles, which is typically derived from the 48 MHz crystal oscillator (See System Clock (SYSCLK) for more information.) The period can be measured over 1-16 asynchronous clock cycles. The number of asynchronous clock cycles measured is controlled by the ASCC_CFG_PERIODS_CFG bit field in the ASCC_CFG register. By using the value stored in the ASCC_PERIOD_CNT register, the period can be calculated as:

NOTE: The accuracy of the period measurement is improved by increasing the ASCC_CFG_PERIODS_CFG value and/or the SYSCLK frequency.

This period counter is supported by:

- The ASCC_CTRL_PERIOD_CNT_START bit from the ASCC_CTRL register, which clears and starts the period counter when a rising edge of the asynchronous clock is detected
- The ASCC_CTRL_PERIOD_CNT_STOP bit from the ASCC_CTRL register, which stops the period counter mechanism manually
- The ASCC_CTRL_PERIOD_STATUS bit, which indicates whether the period counter mechanism is active or idle
- The ASCC_PERIOD interrupt, which is triggered when the asynchronous clock period counter finishes counting the defined number of asynchronous clock periods

The ASCC_PHASE_CNT register measures the time from the synchronization pulse to the first detected rising edge of the asynchronous clock, in terms of SYSCLK cycles. This measurement is used to improve the resolution of the calculated number of asynchronous clock cycles per frame. This counter is supported by:

- The ASCC_CTRL_PHASE_CNT_START bit (in the ASCC_CTRL register), which clears and starts the phase counter the next time a synchronization pulse is generated
- The same register’s ASCC_CTRL_PHASE_CNT_START_NO_WAIT bit, which clears and starts the phase counter immediately
- The same register’s ASCC_CTRL_PHASE_CNT_STOP bit, which stops the phase counter mechanism manually
- The same register’s ASCC_CTRL_PHASE_STATUS bit, which indicates whether the phase counter mechanism is currently active or idle
- The ASCC_PHASE_CNT register, which contains the number of SYSCLK cycles between when the counter started, and when a rising edge has been detected on the asynchronous clock (saturated to 0xFFFF), at which point the counter is stopped automatically
- The ASCC_PHASE interrupt, which is triggered when the phase counter is running and a rising edge occurs on the asynchronous clock, at which point the counter mechanism is stopped automatically

Using the values obtained from the ASCC_CNT and ASCC_PHASE_CNT registers plus the previous period and phase count values, you can calculate the number of asynchronous clock cycles between the previous (i-1) and the current (i) synchronization pulses as follows:

The recommended process for using the measurement registers is as follows:

- Before a synchronization pulse is expected to occur, start the phase counter mechanism.
- When the ASCC_PHASE interrupt occurs:
  1. Save the ASCC_PHASE_CNT counter value from the previous frame.
  2. Record the A SCC_PHASE_CNT counter value.
  3. Record the value in the ASCC_CNT register.
  4. Reset the ASCC_CNT register/counter.
  5. Start the period counter.
- When the ASCC_PERIOD interrupt occurs:
  1. Record the ASCC_PERIOD_CNT counter value.
  2. Calculate the number of SYSCLK cycles per asynchronous clock period.

For registers, see Asynchronous Clock Counter Registers.