## Memory Protection Unit

The Arm Cortex-M33 processor implementation in RSL15 is supported by a protected memory system architecture centered around a memory protection unit (MPU). When used, the MPU provides support for protected memory regions and access permission control. When active, the MPU invokes a MemManage fault when a memory access occurs outside of a valid address that is accessible to the processor in the current system configuration (and execution state).

For information on using the memory protection unit as part of a secure/non-secure application pair, see TrustZone. For more general information on the MPU, refer to the Arm v8-M Architecture Reference Manual and the Arm Cortex-M33 Processor Technical Reference Manual.

IMPORTANT: For best practices in error, fault, and watchdog interrupt handling see Diagnostic Strategies from the RSL15 Developer's Guide.

For this peripheral’s registers, see Memory Protection Unit Registers.