# Pulse Code Modulation (PCM) Interface

RSL15 has access to one pulse code modulation (PCM) interface, which can be used to stream control, configuration or signal data into and out of the microcontroller.

The PCM interface connects to the processor through the Arm Cortex-M33 processor's peripheral bus. There are two possible ways the PCM interface can handle transmission and reception buffers:

| • | By using the internally available data transmission and reception interrupts. These interrupts can be enabled by setting the PCM_CFG_RX_TX_INT_ENABLE bit in the PCM_CFG register.

| • | By connecting to the DMA with two channels supporting transmit and receive operations. The data request lines to the DMA can be enabled by setting the PCM_CFG_TX_DMA_ENABLE and PCM_CFG_RX_DMA_ENABLE bits in the PCM_CFG register.

The "High-Level PCM Interface Module Block Diagram" figure shows a high-level view of the PCM interface.

Figure: High-Level PCM Interface Module Block Diagram

The PCM interface is multiplexed onto the GPIO pads, which can be physically configured for the input and output signals that form the PCM interface. For more information about configuring the multiplexed GPIO functionality, see Functional Configuration.

These interfaces make use of four external signals in communications. These signals are:

| • | An interface clock signal (PCM_CLK)

| • | A bidirectional frame signal (PCM_FRAME)

| • | A serial output data signal (PCM_SERO)

| • | A serial input data signal (PCM_SERI)

CAUTION: Disabling the bus pull-up and pull-down resistors is not recommended for the PCM clock unless this clock is sourced within the RSL15 system. Similarly, disabling the bus pull-up and pull-down resistors is not recommended for the PCM frame signal in slave mode. For all other configurations, attempting to use this interface without the pull resistors can cause unintended interface behavior that would result in the PCM interface transmitting and/or receiving undefined data.

The PCM interface uses the PCM_CTRL_ENABLE bit in the PCM_CTRL register to enable and disable the PCM interface. When using the PCM interface in any mode, set this bit and ensure that the proper GPIO multiplexing has been selected.

NOTE: While the PCM interface is disabled, the internal data registers are held at their current state, and the internal clocks are gated. Enabling the interface resumes the state machine of the interface, and disabling the interface pauses the interface's state machine. Note that the DMA is not gated by the interface enable, so a DMA request can be generated with the PCM interface disabled.

The PCM interface can be configured as either a master device (controlling the frame signal, and potentially providing the interface PCM_CLK through an internally routed GPIO function), or a slave device (receiving the frame signal and usually not providing the PCM_CLK). To select between these configurations, configure the PCM_CTRL_SLAVE bit in the PCM_CTRL register as appropriate. In master mode, configure the PCM frame signal as an output; in slave mode, configure it as an input. The PCM clock signal is always an input to the PCM interface; this clock signal can be sourced in the following ways:

| • | Internally, selecting a clock source as the GPIO output mode for the pad that is also used for the PCM clock, to route an internal clock signal within the RSL15 system to the same pad

| • | Externally, using an externally generated clock signal

The PCM clock frequency can be the same as the system clock frequency. External clocks can also be used to drive the PCM interfaces; these clocks can be sourced via an external PCM device, or one of the output clocks from the RSL15 system can be used (e.g. USRCLK).

The PCM interface is sensitive to only one edge of the PCM clock. All settings are clocked in and signal updates are captured on the rising or falling edge, as specified by the PCM_CFG_CLK_POLARITY bit from the PCM_CFG register. By default, the PCM interface samples its inputs on the falling edge of the PCM clock, outputting its signals on the rising clock edge. When configuring the PCM interface for I2S standard compatibility mode, we recommend that you configure the interface to sample on the rising edged of the clock. This is done by setting the PCM_CFG_CLK_POLARITY bit in the PCM_CFG register.

A PCM interface can be reset using the PCM_CTRL_RESET bit from the PCM_CTRL register. This resets the internal data registers, clocks, and state machine on the next PCM clock edge. Reset the interface to restart in a known good state after any error is detected.

IMPORTANT: The PCM interface configuration and internal status registers are tightly synchronized to the input PCM clock. As a result, the PCM interfaces are only reset, and the internal configurations of the PCM interfaces are only updated, on their selected PCM clock edges.

## PCM Signal Configuration

The PCM interface uses a large number of configuration options to help define a set of signals that the system can interpret. For the purpose of clarifying the following explanations, the signals generated by the system in the default PCM configuration are shown in the "Signal Timing Diagram: Default PCM Configuration" figure, below.

Figure: Signal Timing Diagram: Default PCM Configuration

For more information about the required signal configuration and other interface configurations that are needed for interface compatibility with I2S, including an example timing diagram, see I2S Configuration and Usage.

IMPORTANT: To ensure defined behavior, the PCM interface needs to be in IDLE state when changing any configuration settings.

### Frame Signal Configuration and Timing

The PCM interface uses a signal, called a frame signal, to realign transmission over the PCM interface between two devices with every data frame transmitted.

The frame signal divides the communications on the PCM interface into data frames (or sub-frames, if the PCM_CFG_SUBFRAME bit of the PCM_CFG register is enabled). Each aspect of the PCM frame signal can be configured as follows (all bits are in the PCM_CFG register):

Interval

In the default configuration of the PCM_CFG_FRAME_LENGTH bit field (configured for two words per frame) and the PCM_CFG_SUBFRAME bit (configured to disable a frame signal being generated for each word within a frame), the frame signal is generated once for every two-word frame. Changing the PCM_CFG_FRAME_LENGTH bit field in PCM master mode allows the user to select the number of words per frame, incrementing in multiples of two words, and therefore the number of words per data frame. The PCM_CFG_FRAME_LENGTH bit field is not used for PCM slave mode; it needs to be left in the default configuration (configured for two words per frame), regardless of the actual frame length used, to produce the expected behavior. If the PCM_CFG_SUBFRAME bit is configured to enable sub-frames, a frame signal is generated with every word of each data frame.

IMPORTANT: Configuring the PCM_CFG_FRAME_LENGTH bit field to something other than two words per frame, when setting the PCM_CFG_SUBFRAME bit, results in a configuration where the user receives a PCM frame signal for every sub-frame word. Despite the well-defined behavior of the frame signal generated for this configuration, the handling of data and interrupts by the PCM interfaces might not appear sensible and generally results in undefined or unexpected data.

Shape

The frame signal can be configured to take one of two shapes, by setting the PCM_CFG_FRAME_WIDTH bit. By default, the frame signal is configured to produce a short width frame signal, which produces a single cycle pulse in the frame signal at the beginning of each frame. Alternatively, you can configure the signal to produce a long width frame signal, which uses a 50% duty cycle square wave and is spaced to align with the specified width between frame signal events.

Alignment

You can configure the PCM_FRAME signal by using the PCM_CFG_FRAME_ALIGN bit, so that the first bit of sampled data is sampled at the same time as the frame signal, or the first bit of data is sampled one cycle after the frame signal. In this way, the frame signal is aligned with the first bit of the new data frame, or with the last bit of the previous data frame.

NOTE: Regardless of the PCM_FRAME signal alignment configuration, the PCM_FRAME signal occurs at the beginning of each frame, and only one frame signal occurs for each frame received. The PCM_FRAME signal, if aligned with the last bit, occurs one bit before the first data bit transmitted at the start of a transaction, and does not occur on the last bit of the last frame of a transaction. Similarly, if aligned with the first bit, the first frame signal is aligned with the first data bit transmitted at the start of a transaction, and no trailing frame signal occurs for a transaction.

IMPORTANT: To properly terminate a transmission, an expected frame signal pulse must be missed. When the frame signal is configured to be aligned with the first bit of a transmission, this requires one additional PCM_CLK pulse following the transmission of the last bit of the last frame.

For clarification of the above PCM_FRAME signal timing configuration explanations, several examples of different PCM_FRAME signal traces are shown in the "Frame Signal Timing Examples" figure. In all cases, the PCM_CFG_FRAME_ALIGN bit has been set to PCM_FRAME_ALIGN_FIRST (which differs from the default configuration shown in the "Signal Timing Diagram: Default PCM Configuration" figure), to prevent any confusion as to the effects of the other frame signal configuration bits. The frame signal configurations shown are:

| 1. | Configured to indicate the sub-frame words of a frame with a short pulse frame signal

| 2. | Configured to indicate the sub-frame words of a frame with a long width frame signal

| 3. | Configured to use a 2-word frame with a short pulse frame signal

| 4. | Configured to use a 2-word frame with a long width frame signal

| 5. | Configured to use a 4-word frame with a short pulse frame signal

| 6. | Configured to use a 4-word frame with a long width frame signal

Figure: Frame Signal Timing Examples

The "PCM Frame Signal Configuration Options" table summarizes the options for PCM_FRAME signal configuration.

Table: PCM Frame Signal Configuration Options

Configuration Option | Settings | Description
Sub-frames (Master mode only) | Sub-frames disabled (default), sub-frames enabled | When sub-frames are enabled, the PCM interface provides a frame signal for every word in the frame.
Frame Size | 2 (default), 4, 6, 8, 10, 12, 14 or 16 words by frames | Specifies the number of words that are expected in each frame (only applicable when sub-frames are disabled).
Frame signal width | Short (default), Long | A short PCM frame signal is held high for one PCM clock cycle. A long PCM frame signal is held high for one half of the PCM frame.
| NOTE: | If sub-frame is enabled and the word size is odd, the frame signal is held high for a portion of the frame equal to half of the word size rounded down.
Alignment | Align to first data bit, align to last data bit (default) | The first (and possibly only) cycle in which the PCM frame signal is high; it is aligned with the specified data bit (default)

### Data Serial Input and Output Configuration

The PCM interface allows data bits to be configured for transmission and reception in either an MSB first or an LSB first ordering. To select between these two configurations, set the PCM_CFG_BIT_ORDER bit in the PCM_CFG register.

The length of each word of a PCM transaction can be set to be between 8 and 32 bits per word, by setting the PCM_CFG_WORD_SIZE bit field in the PCM_CFG register. When transmitting data that uses less than 32 bits per word, the PCM_CFG_TX_ALIGN bit from the PCM_CFG register configures whether the data is loaded from the most significant portion of the data register, or from the least significant portion of the data register (both configurations are equivalent when using 32-bit data words).

The "PCM Data Configuration Options" table summarizes the options available for data configuration.

Table: PCM Data Configuration Options

Configuration Option | Settings | Description
Data ordering | MSB first (default), LSB first | Selects whether the data is transmitted starting with the MSB or LSB
Word size | 8- to 32-bit (default) by words | Specifies the number of bits in each PCM word
Transmit and receive bit-field | MSB bit-field (default), or the LSB bit-field | Selects the data alignment (MSB or LSB)

## PCM/I 2S Data Interface

Each PCM interface has two single word transmit registers called PCM_TX_DATA*, and two single word receive registers called PCM_RX_DATA*. The first word received after the rising edge of the frame is stored in the PCM_RX_DATA0 register, and the second word is stored in the PCM_RX_DATA1 register. Similarly, the PCM_TX_DATA0 register is transferred first, followed by the PCM_TX_DATA1 register.

If the word size is greater than 2, both receive registers are overwritten with the next words, and the data in both transmit registers is sent. The order of capture and send is always the same.

NOTE: There are always two words transmitted or received per frame, never only one.

## PCM Interrupt Configuration

Each PCM interface uses two associated interrupts. These interrupts control transmission and reception of PCM data, and report any errors that have occurred while transmitting or receiving PCM data. These interrupts can be configured by setting the PCM_CFG_RX_TX_INT_ENABLE, PCM_CFG_OVERRUN_INT_EN, and PCM_CFG_UNDERRUN_INT_EN bit fields in the PCM_CFG register. See Nested Vector Interrupt Controller (NVIC) for information regarding interrupt configuration and handling interrupts for the Arm Cortex-M33 processor.

If a user application is transmitting data from a PCM interface, the PCM_RX_TX interrupt sends signals at the following times:

| • | When the PCM_TX_DATA* registers' value starts to be transmitted using the PCM interface

| • | When the PCM_STATUS_TX_REQ bit of the PCM_STATUS register is set, signifying that the next data word(s) (of the specified size) to be transmitted can now be loaded into the PCM_TX_DATA* registers by the application

| • | When the PCM_STATUS_RX_REQ bit of the PCM_STATUS register is set, signifying that a data word(s) of the specified size has been successfully received and written to the PCM_RX_DATA* registers

The PCM transmit and receive interrupts are generated for every two words of data transmitted in a valid PCM frame, regardless of the length of the PCM frame. The data register that acknowledges the transmission or reception can be configured by setting the PCM_CFG_TX_ACK_SEL and PCM_CFG_RX_ACK_SEL bit fields of the PCM_CFG register.

The PCM_ERROR interrupt indicates one of the following conditions:

| • | An overrun has occurred: the received data from the PCM_RX_DATA* registers has not been read before being overwritten. The PCM_STATUS_OVERRUN bit in the PCM_STATUS register can be read for overrun status.

| • | An underrun has occurred: new data has not been copied to the PCM_TX_DATA* registers before the occurance of the next PCM transmission. The PCM_STATUS_UNDERRUN bit in the PCM_STATUS register can be read for underrun status.

NOTE: The status bits for overrun and underrun errors in the PCM_STATUS register can be cleared by setting the associated clear bits in the same register.

The "PCM Interrupt Options" table summarizes the options available for PCM interrupt configuration.

Table: PCM Interrupt Options

Interrupt Type | Signal Name | Status Register Name | Description
Data received | pcm_rx_tx_irq | RX_REQ_STATUS | Interrupt when a new data word is ready to be read by processor
Data sent | TX_REQ_STATUS | Interrupt when a data word has been sent, transmit register is ready for a new value
Overrun detected | pcm_err_irq | OVERRUN_STATUS | A new data word has been received on the interface before the last received data has been read
Underrun detected | UNDERRUN_STATUS | A new data word has been sent on the interface before previous data has been written on the transmit register

## I 2S Configuration and Usage

The PCM interface can be configured to be compatible with the I2S interface standard. The "Required Configuration Settings for I2S Configuration" table lists the required signal and data management settings for the PCM interface to enable I2S communication.

Table: Required Configuration Settings for I2S Configuration

Configuration Bit or Bit Field | Setting
PCM_CFG_FRAME_LENGTH | PCM_MULTIWORD_2
PCM_CFG_FRAME_WIDTH | PCM_FRAME_WIDTH_LONG
PCM_CFG_FRAME_ALIGN | PCM_FRAME_ALIGN_LAST
PCM_CFG_BIT_ORDER | PCM_BIT_ORDER_MSB_FIRST
PCM_CFG_SUBFRAME | PCM_SUBFRAME_DISABLE
PCM_CFG_CLK_POLARITY | PCM_SAMPLE_RISING_EDGE 1 The PCM interfaces produce a data stream that is I2S standard compliant with either sampling edge. However, to comply completely with the standard, the interface must be configured to sample data on the rising edge of the clock.

In master mode, the I2S configuration for the PCM interface has no effect.

In slave mode, the behavior of the PCM interfaces is slightly different from how it acts in any other configuration. When configured for slave mode and a long frame width, the PCM interfaces synchronize communications with both the rising edge and falling edge of the frame signal (instead of synchronizing with only the rising edge as it does in all other configurations). This means that if the word size used by the master is larger than the size configured in the corresponding PCM interface, the interface pads the remaining bits with zeroes for both words. If the size is less than the size configured, the interface only sends and receives the MSB bits of both words.

As shown in the I2S signal timing diagram (see the "Signal Timing Diagram: I2S Configuration" figure), after transmitting the LSB of the current data word, the device repeatedly transmits zeros until a rising or falling edge on the frame signal is detected. Similarly, if a rising or falling edge is detected on the frame signal before the current data word has been completely transmitted, the current data word is truncated and the next data word is sent. In this way, the interface is compatible with I2S signals that transmit a number of bits different from the number specified in the defined word size.

Figure: Signal Timing Diagram: I2S Configuration

For registers, see PCM Registers.