# I2C Interfaces

The I2C interfaces are compatible with the UM10204 I2C specification. I2C uses a two-wire interface that includes a bidirectional clock line (SCL) and a bidirectional data line (SDA). The I2C interfaces are typically used for communication with external sensors and storage devices, and as control signals for radios.

The I2C interfaces support both master and slave mode operation, and can be configured to connect to the DMA master through a DMA channel to support moving data without processor intervention. There are two interfaces on RSL15—I2C0 and I2C1—and the description that follows applies to both of them.

NOTE: Each I2C interface has its own set of registers. In the text below, a reference to an I2C*_XXX register (ex., I2C*_CFG) refers to the I2C0 and I2C1 versions of this register.

For information about configuring the GPIOs for the I2C interface, see I2C.

IMPORTANT: I2C interfaces are defined using open-collector pads for the I2C bus. Because these pads do not drive a high signal for the bus signals—relying on the bus's pull-up resistors for proper operation—user applications working with this interface must use either the internal pull-up resistors implemented for the GPIO pads, or a set of external pull-up resistors on the GPIOs assigned to be the I2C bus lines.

The I2C interface uses the rising edges of a serial clock signal (SCL) to clock in data from a serial data signal (SDA) to communicate between devices. The I2C interface is designed to handle bus traffic operating at up to 1 MHz.

The example timing diagram shown in the "I2C Signal Timing Diagram" figure provides information about the important elements in an I2C transaction, which are described in further detail in the previously mentioned bus specification. These elements are:

Start Condition

The SDA transitions from the idle high state to the low state while the SCL remains high. This can also happen during a transmission as a repeated start condition, indicating that the transaction is starting again without an intermediate stop condition.

Address Bits

During the first byte transmitted, the first seven bits on the SDA (clocked in on a rising edge of SCL) provide the address of the device with which the master device wants to communicate. A device that is properly addressed needs to acknowledge this transaction if communications are to conform to the I2C standard.

Read/Write Direction Bit

During the first byte transmitted, the eighth bit on the SDA (clocked in on a rising edge of SCL) indicates the direction of the transaction. A zero for this bit indicates a write by the master; a one indicates a read by the master. If the master device has requested a read, the slave device controls the SDA line on subsequent bytes to transmit data.

Data Byte

All other bytes, excluding the addressing and read/write byte, that are transmitted on the SDA are considered data bytes for the transaction.

Acknowledge or Not Acknowledge Bit

The acknowledge bit is used to indicate to the sender that the byte has been received. The device receiving data needs to acknowledge each data byte (ACK), including the address byte. During this time, the bus device that is sending data on the data bus stops driving the SDA and allows the line to be pulled high. To not acknowledge a byte (NACK), the receiving device does not respond. To ACK, the receiving device needs to pull the SDA low. A receiving slave device needs to NACK if the slave device is not the device that has been addressed, or if the device cannot handle the byte received. A master device needs to NACK if the master is receiving and wants to end the transaction. If a NACK is encountered, the device transmitting data needs to generate a stop condition.

Stop Condition

The SDA transitions from a low state to high state while the SCL remains high. This ends an I2C transaction.

Figure: I2C Signal Timing Diagram

The I2C*_CTRL registers are the interface control registers. They contain write-only control bits and read-only status bits to indicate the status of key control settings. Each of the write-only bits is used to trigger an event. Information about these bits is summarized in the "I2C Control Bits" table.

Table: I2C Control Bits
Bit Field | Field Name | Field Description
--- | --- | ---
9 | I2C_CTRL_LAST_DATA_STATUS | Read-only bit indicating if the current byte is the last data byte for a transfer
8 | I2C_CTRL_ENABLE_STATUS | Read-only bit indicating that an I2C interface is enabled or disabled
6 | I2C_CTRL_LAST_DATA | Indicate that the current data is the last byte
5 | I2C_CTRL_STOP | Issue a stop condition on the I2C interface
4 | I2C_CTRL_NACK | Issue a negative acknowledgment of a sent/received byte.
3 | I2C_CTRL_ACK | Issue an acknowledgment of a sent/received byte. Resume I2C internal state machine
2 | I2C_CTRL_RESET | Reset the I2C interface
1 | I2C_CTRL_DISABLE | Disable the I2C interface
0 | I2C_CTRL_ENABLE | Enable the I2C interface

The I2C*_STATUS registers contain bits that are defined as read-only event bits, state bits, or write-only control bits used for updating the state of the I2C interface. The event bits are used to indicate that an event has occurred, and the state bits are used to indicate an interface operating state. Information about these status bits is shown in the "I2C Event and State Status Bits" table.

Table: I2C Event and State Status Bits
Bit Field | Field Name | Bit Type | Field Description
--- | --- | --- | ---
26 | I2C_STATUS_STOP_OR_REPEATED_START_DETECTED | Event | Indicate if a stop or repeated start has been detected
25 | I2C_STATUS_REPEATED_START_DETECTED | Event | Indicate if an I2C repeated start has been detected during an active transaction in slave mode
22 | I2C_STATUS_BUS_ERROR | State | Indicate that a bus error or conflict has occurred during transmission
21 | I2C_STATUS_BUSY | Event | Indicate that the reception or transmission of the data is ongoing
20 | I2C_STATUS_START_PENDING | Event | Master frame start pending status bit
19 | I2C_STATUS_MASTER_MODE | Event | Master mode status bit
18 | I2C_STATUS_STOP_DETECTED | Event | Indicate if an I2C stop bit has been detected
17 | I2C_STATUS_DATA_EVENT | State | Indicate that an I2C interface either needs data to transmit or has received data
16 | I2C_STATUS_TX_REQ | State | Indicate that a TX data can be written
15 | I2C_STATUS_RX_REQ | State | Indicate that an RX data byte is ready to be read
14 | I2C_STATUS_CLK_STRETCH | State | Indicate that the I2C clock (SCL) is being stretched
13 | I2C_STATUS_LINE_FREE | State | Indicate that the I2C bus is free
12 | I2C_STATUS_ADDR_DATA | State | Indicate if the information sent on the bus is an address or data byte
11 | I2C_STATUS_READ_WRITE | State | Indicate if the current I2C transaction is a read or a write
10 | I2C_STATUS_GEN_CALL | State | Indicate if the current I2C transaction used the general call address or the interface's regular address
9 | I2C_STATUS_ACK | State | Indicate if the data has been acknowledged (ACK) or not-acknowledged (NACK)
8 | I2C_STATUS_OVERRUN | State | Indicate that an overrun has occurred when receiving data
4 | I2C_STATUS_TX_REQ_SET | Control | Write 1 to set the TX_REQ status flag, flushing the current contents of the transmit buffers
3 | I2C_STATUS_REPEATED_START_DETECTED_CLEAR | Control | Write 1 to clear the REPEATED_START_ DETECTED status flag
2 | I2C_STATUS_STOP_DETECTED_CLEAR | Control | Write 1 to clear the STOP_DETECTED status flag
1 | I2C_STATUS_BUS_ERROR_CLEAR | Control | Write 1 to clear the BUS_ERROR status flag
0 | I2C_STATUS_OVERRUN_CLEAR | Control | Write 1 to clear the OVERRUN status flag

NOTE: The interfaces support both master and slave operations, which can be simultaneously enabled. A user application can use the interface in both modes, provided the application ensures that the I2C bus is not currently in use. When attempting to initialize a transfer as a master device, check the I2C_STATUS_LINE_FREE bit in the I2C*_STATUS registers to verify that the I2C bus is not currently in use..

IMPORTANT: When multiple masters co-exist on the bus, an I2C*_STATUS_BUS_ERROR is detected if the bit driven onto the serial data line is different from the data read from the serial data line. As soon as a BUS_ERROR is detected, the I2C interface stops driving the SCL and SDA lines, and an interrupt is generated if the BUS_ERROR_INT_ENABLE bit is set. The BUS_ERROR bit remains asserted until the SDA line is released by the other devices on the bus. A user application needs to wait for the bus to be free again and issue a stop condition to reset the slaves connected on the bus.

The I2C interfaces use the I2C*_TX_DATA and I2C*_RX_DATA registers to respectively transmit and receive data. The I2C interfaces use the I2C*_STATUS_TX_REQ and I2C*_STATUS_RX_REQ bits in the I2C*_STATUS registers to request data for transmission and to indicate when a new byte is available to be read. Writing to and reading from I2C*_TX_DATA and I2C*_RX_DATA automatically clears the corresponding *TX_REQ bit or RX_REQ bit (respectively) in hardware. As use of the I2C*_RX_DATA registers can advance the I2C interface state machine, these registers are mirrored in the I2C*_RX_DATA_MIRROR registers without impacting the I2C state machine. Reading from these registers does not clear the I2C*_STATUS_RX_REQ bit in the I2C_STATUS register. A write only bit called I2C*_STATUS_REQ_SET in the I2C_STATUS register can be used to set the I2C*_STATUS_TX_REQ register and discard the current data in the buffer.

NOTE: The I2C*_STATUS_TX_REQ status flag is useful in slave mode, when a master ends a transaction and forces a stop condition (I2C). At this point the TX_REQ flag is zero, which indicates that there is still a byte pending in the TX buffer. To clear this state without resetting the interface, set I2C*_STATUS_TX_REQ_SET high to request new data again. This does not generate a new interrupt (TX); only the underlying buffer is flushed.

Each byte of an I2C transaction must be ACK or NACK. Use the I2C*_CFG_AUTO_ACK_ENABLE bit from the I2C*_CFG registers to select whether the application handles this acknowledgment manually, or the interface handles it automatically. In either case, if the application does not provide data in time or move the interface's internal state machine forward, the transaction is paused by stretching the clock signal until the interface can continue. If the clock is being stretched, the I2C*_STATUS_CLK_STRETCH bit from the I2C*_STATUS register is set as an indicator. Use of the above mentioned data registers and the general behavior of the I2C state machine is described in Operation Using Manual Acknowledgment for manual acknowledgment mode, and in Operation Using Automatic Acknowledgment for automatic acknowledgment mode.

NOTE: If, at any point when operating in either master or slave mode, a user application needs to reset the I2C bus lines (for example, after encountering a bus error condition), the application needs to write the I2C_CTRL_RESET bit from the I2C_CTRL register. This resets both the I2C bus and the internal state machines of the I2C interface, allowing the system to cleanly start again from a known state.

## Slave Mode Specific Configuration

In slave mode, the device is receiving the serial clock signal from an external master device, which also controls addressing, direction, and the start/stop conditions for each I2C transfer. For communications to proceed on the I2C interface, the following relation between the system clock (which is used internally to clock the I2C interface) and the SCL must hold:

When in slave mode, the I2C interfaces can be held while waiting for data to be read, or for new data to be available for transmission. In this case, the SCL line is held low by the slave interface—stretching the clock. The I2C_CFG_SLAVE bit fields in the I2C*_CFG registers are used to configure the settling time required for the SDA line, by selecting the number of SYSCLK cycles between the time when data is put on the SDA line and when the SCL line is released. It is important that the software be able to keep up with data transmitting from the master at the full rate (1 Mbps in Fast-mode Plus), to minimize the overhead due to clock stretching. For more information, see Setting the System Clock.

To enable a device in slave mode, set the I2C_CFG_SLAVE bit from the appropriate I2C*_CFG register. Both master and slave operation can be enabled at the same time. The application can use the I2C_STATUS_MASTER_MODE bit field to identify which state machine is active when an action is being requested by the interface. The device responds to communications on both the I2C general call address (0x00; I2C write transactions only) and at a programmable slave address that can be selected using the I2C_CFG_SLAVE_ADDRESS bit fields in the I2C*_CFG registers. During a transaction, the I2C_STATUS_GEN_CALL bit in the appropriate I2C*_STATUS register can be queried to identify the addresses that were used to address the device.

A device receiving data in a slave mode configuration can use the I2C_CTRL_LAST_DATA bit from the appropriate I2C*_CTRL register to automatically NACK the last data byte, to indicate to a master device that it needs to send a stop condition.

NOTE: The I2C_CTRL_LAST_DATA bit is cleared when a stop condition is received.

## Master Mode Specific Configuration

In master mode, the device provides the serial clock signal and controls all transfer information. To configure the clock signal, you need to select a prescaling division by 3 using the I2C_CFG_MASTER_PRESCALE bit field in the appropriate I2C*_CFG register. The interface clock frequency for a given configuration can be calculated using this formula:

NOTE: The System clock needs to be set to at least 1.5 MHz for Fast-mode (400 kbps), and at least 6 MHz for Fast-mode Plus (1 Mbps). For more information, see Setting the System Clock

A user application must manually control all components of a master mode transaction. To transmit or receive using master mode, a device must:

1. Check that the I2C bus lines are not currently in use, by reading the I2C_STATUS_LINE_FREE bit in the appropriate I2C*_STATUS register. The device can only start a transaction if the lines are free.
2. Start a transaction, sending the start condition, address, and direction, by loading the appropriate address and direction to the I2C*_ADDR_START register.
3. Handle data and interrupts as appropriate for the transaction (see I2C Interrupts).
4. Complete the transaction by sending a stop condition. A stop condition can be generated using either the I2C_CTRL_STOP bit or the I2C_CTRL_LAST_DATA bit in the I2C*_CTRL registers.

When using the I2C_CTRL_LAST_DATA bit, a stop condition is automatically generated after the current data byte transfer is completed. If the interface is receiving data, this bit also automatically generates the required NACK of the last data byte that is received. Multi-master mode can be supported in software by handling the BUS_ERROR status bit, which is set when a conflict occurs. The arbitration procedure and clock synchronization are active in master mode.

NOTE: If the I2C interface is used for transmitting, the last byte of data to be transmitted must be written to the I2C_DATA register before setting the I2C_CTRL1_LAST_DATA bit, as this bit triggers a stop condition at the end of the current transfer.

NOTE: The I2C_CTRL1_LAST_DATA bit is cleared when a stop condition is received on the I2C bus.

When using the I2C_CTRL_STOP bit, a stop condition is issued immediately. This bit is normally set when the I2C_CTRL_ACK bit or I2C_CTRL_NACK bit in the I2C_CTRL register is set. In master mode, a stop condition is automatically generated if data or an address has not been acknowledged by the slave.

CAUTION: Using the stop event (STOP) immediately transmits a stop condition as soon as possible. This can result in a terminated transfer, and remote devices on the bus might detect I2C errors.

The following list shows the interrupt triggers which can be enabled, and the reasons why they would be triggered:

| • | TX_INT_ENABLE (triggered when a byte is transmitted)

| • | RX_INT_ENABLE (triggered when a byte is received)

| • | BUS_ERROR_INT_ENABLE (triggered when a bus error occurs)

| • | OVERRUN_INT_ENABLE (triggered when any data has been received that has overwritten the RX data buffer before the data in the buffer could be read)

| • | STOP_INT_ENABLE (triggered when a stop event occurs)

| • | REPEATED_START_INT_ENABLE (triggered when a repeated start event occurs)

## Setting the System Clock

A maximum transmission rate of 400 kbps (Fast-mode) is fully supported by the I2C interface. In this mode, the system clock must be set to at least 1.5 MHz for Fast-mode (400 kbps) for a system with a sufficient pull-up resistance on SDA to provide a pull-up time of less than 150 ns.

A maximum transmission rate of 1 Mbps (Fast-mode plus) is supported, with the exception of the pad drive strength required by the I2C standard (20 mA at 0.4 V). Multiple GPIO pads can be used in parallel to increase the drive strength, but this might not be sufficient to meet the specifications, especially at low VDDO. In this mode, the sytem clock must be set to at least 6 MHz for Fast-mode Plus (1 Mbps) for a system with a sufficient pull-up resistance on a reasonably fast SDA to provide a pull-up time of less than 100 ns.

## I2C Interrupts

The I2C interfaces use associated interrupts which, when enabled, signal the receipt of a correct address byte and the completion of each data byte in the transaction. Interrupts can also be enabled to identify bus-related conditions, such as bus errors during arbitration, stop conditions on the bus, and repeated start conditions (in slave mode only). In addition, the buffer overrun interrupt is available to identify firmware issues.

See Nested Vector Interrupt Controller (NVIC) for information regarding interrupt configuration and handling interrupts for the Arm Cortex-M33 processor.

Several status indicators from the I2C*_STATUS registers can be used with the interrupt to identify the state of the I2C interface:

| • | If the I2C_STATUS_ADDR_DATA bit is set, the interrupt has been generated in response to a recognized sequence, including a start condition and address on the I2C interface. No interrupt is generated for I2C transactions that use an address which has not been recognized by the I2C interface.

| • | If the I2C_STATUS_STOP_DETECTED bit is set, the interrupt has been generated in response to a stop interrupt being a condition for an active transaction on the I2C interface. To clear the status of this bit, write a 1 to the I2C_STATUS_STOP_DETECTED_CLEAR bit.

| • | If the I2C_STATUS_DATA_EVENT bit is set, the interrupt indicates that data has been received and can be read, or that data is needed in order to continue with the data transmission.

| • | If the I2C_STATUS_BUS_ERROR bit is set, then a bus error has occurred.

| • | If the REPEATED_START_DETECTED bit is set, a repeated start condition has been detected by the device. This interrupt occurs during an active transaction in slave mode.

### Operation Using Manual Acknowledgment

If an application is using manual acknowledgment (i.e., the I2C*_CFG_AUTO_ACK_ENABLE bit from the I2C*_CFG registers is disabled), the application needs to use the I2C_CTRL_NACK and I2C_CTRL_ACK bits from the I2C*_CTRL registers to acknowledge (ACK) or not-acknowledge (NACK) transaction bytes.

When handling a transaction, an interrupt is issued whenever data or an acknowledgment is required (in addition to interrupts triggered by stop conditions).

NOTE: An interrupt is not generated following a NACK for any data condition. However, an interrupt is generated (if operating in master mode or if stop interrupts are enabled) on the stop condition that is expected to follow the NACK.

A special interrupt is also generated for a master read, once the acknowledge bit from the address byte has been received. This scenario is a special case: it does not require data nor acknowledgment to trigger an interrupt, but instead is designed to allow the interface to check whether or not a slave device has acknowledged the transfer at that point. Provided the slave device has responded, the interface can issue a resume command by writing a 1 to the I2C_CTRL_RESUME bit command, which continues the transfer.

NOTE: Use of the I2C_CTRL_NACK, I2C_CTRL_ACK and I2C_CTRL_STOP bits from the I2C*_CTRL registers is only defined when an acknowledgment is needed during a data transfer. Interface behavior in response to these control bits being set at other times is undefined.

### Operation Using Automatic Acknowledgment

When operating using auto acknowledgment (i.e., the I2C_CFG_AUTO_ACK_ENABLE bit from the appropriate I2C*_CFG register is enabled), transfers are controlled by the availability of bytes for transmission, or a place to put a byte when receiving data. This allows transfers to occur without clock stretching, if the firmware is able to handle each data byte fast enough. A DMA channel can be used in auto acknowledgment mode to reduce CPU utilization.

NOTE: DMA-based transfers are only supported in auto acknowledge mode.

When the interface handles a transaction, interrupts are issued whenever new data can be written or new data has been received. This allows a user application to maintain a transaction without introducing delay.

NOTE: An interrupt is not generated following a NACK for any data condition. However, an interrupt is generated (if operating in master mode or if stop interrupts are enabled) on the stop condition that is expected to follow the NACK.

Additionally, interrupts are generated if data has been supplied but cannot be sent because the interface has received a NACK from the slave device, or is currently idle (for instance, after a stop condition). If data is required but is not currently available because the buffer is empty, the clock is stretched and an additional interrupt is generated. If new data has been received but the previous data has not been read (resulting in the buffer not being available), the clock is stretched until the buffer becomes free.

IMPORTANT: When receiving data in master mode, the timing of interrupts for auto acknowledgment of data prevents a user application from cleanly terminating a transfer using the LAST_DATA event. As a result, if the interface is running in this mode, a dummy byte must be transferred to cleanly terminate the current transfer, with a stop condition following this byte.

### I2C Main Modes of Operation

The operation modes of the I2C interfaces fall into two different categories: master modes, and slave modes. The "I2C Slave Modes of Operation" table and the "I2C Master Modes of Operation" table show the master modes of operation and slave modes of operation, respectively, along with details of how they function.

Table: I2C Slave Modes of Operation
Mode | Auto ACK Off, Write Frame | Auto ACK, Read Frame | Auto ACK On, Write Frame | Auto ACK On, Read Frame
--- | --- | --- | --- | ---
Start | Receive start, interrupt if repeated start and repeated start interrupt are enabled | Receive start, interrupt if repeated start and repeated start interrupt are enabled | Receive start, interrupt if repeated start and repeated start interrupt are enabled | Receive start, interrupt if repeated start and repeated start interrupt are enabled
Addr | Receive addr | Receive addr | Receive addr | Receive addr
Ack | Interrupt if addr is matched, stretch clock until ACK/NACK, send ACK/NACK | Interrupt if addr is matched, stretch clock until ACK/NACK, send ACK/NACK | ACK if addr is matched | ACK if addr is matched
Data0 | Receive RX data | Interrupt if TX data not available, stretch until TX data available, send TX data | Receive RX data | Interrupt if TX data not available, stretch until TX data available, send TX data, interrupt
Ack | Interrupt, stretch clock until ACK/NACK, send ACK/NACK | ReceiveACK/NACKfrom remote | Interrupt, stretch clock until RX data is read, ACK | Receive ACK/NACK from remote
Data N | Receive RX data | Interrupt if TX data not available, stretch until TX data available, send TX data | Receive RX data | Interrupt if TX data not available, stretch until TX data available, interrupt, send TX data
Ack N | Interrupt, stretch clock until ACK/NACK, send ACK/NACK | Receive ACK/NACK from remote | Interrupt, stretch clock until RX data is read, ACK | Receive ACK/NACK from remote
Stop | Receive stop, interrupt if stop interrupt is enabled | Receive stop, interrupt if stop interrupt is enabled | Receive stop, interrupt if stop interrupt is enabled | Receive stop, interrupt if stop interrupt is enabled

Table: I2C Master Modes of Operation
Mode | Auto ACK Off, Write Frame | Auto ACK, Read Frame | Auto ACK On, Write Frame | Auto ACK On, Read Frame
--- | --- | --- | --- | ---
Start | Send start | Send start | Send start | Send start
Addr | Sendaddr | Sendaddr | Sendaddr | Sendaddr
Ack | Receive ACK/NACK | Receive ACK/NACK | Receive ACK/NACK | Receive ACK/NACK
Data0 | Interrupt, stretch clock until resume, receive RX data | Interrupt if TX data not available, stretch clock until TX data available, send TX data | Receive RX data | Interrupt if TX data not available, stretch clock until TX data available, interrupt, send TX data,
Ack | Interrupt, stretch clock until ACK/NACK, send ACK/NACK | Receive ACK/NACK from remote | Interrupt, stretch clock until RX data is read, ACK | Receive ACKk/NACK from remote
Data N | Receive RX data | Interrupt if TX data not available, stretch clock until TX data available, send TX data | Receive RX data | Interrupt if TX data not available, stretch clock until TX data available, interrupt, send TX data
Ack N | Interrupt, stretch clock until ACK/NACK, send ACK/NACK | Receive ACK/NACK from remote | Interrupt, stretch clock until RX data is read, ACK | Receive ACK/NACK from remote
Stop | Sendstop, interrupt, interrupt if stop interrupt is enabled | Sendstop, interrupt, interrupt if stop interrupt is enabled | Send stop, interrupt, interrupt if stop interrupt is enabled | Sendstop, interrupt, interrupt if stop interrupt is enabled

For registers, see I2C Registers.