# Overview

The RF front-end communicates with:

- The CPU and the DMA, through a dedicated bridge that accesses the RF front-end internal configuration registers. The CPU always has priority over the DMA. A read operation inserts two wait states and additional wait states are inserted when an SPI operation is active. A write operation inserts two or more wait states depending on various factors, and additional wait states are inserted when an SPI operation is active. Note that the SPI interface has priority over the APB interface.
- The CPU via 6 interrupts.
- The Arm Cortex-M33 processor (CPU), which uses a simple baseband to provide packet handling, and data transfers (supported by interrupts and GPIOs as proprietary debug resources). This mode of operation can be used to implement custom protocols.
- The baseband controller, through the internal SPI interface and dedicated CLK and DATA signals. All these signals are multiplexed through the GPIO block. This mode of operation is used along with provided SW Bluetooth Low Energy stack as part of the RSL15 SDK.

IMPORTANT: Simultaneous RF front-end accesses from the Arm Cortex-M33 processor/DMA and the internal SPI (baseband controller) are prohibited. It is the user's responsibility to ensure that no SPI transaction is ongoing when accessing the RF front-end with the Arm Cortex-M33 processor/DMA.

The Arm Cortex-M33 processor, the DMA (through the APB bus), and the internal SPI interface all have access to the RFFE registers. However, the user application must ensure that no SPI transaction is ongoing when accessing the RFFE over the APB bus. The RF is powered by the VDDRF and VDDC regulators. Digital part of RFFE is powered through VDDC when a power switch is closed through the SYSCTRL_RF_POWER_CFG register, and access is granted through the SYSCTRL_RF_ACCESS_CFG register. The analog part is powered when VDDRF is enabled.

The simplified block diagram of RFFE is shown in the "RFFE Block Diagram" figure.

Figure: RFFE Block Diagram

The digital block of the RFFE contains a full transceiver with the following features:

- FSK modem with programmable pulse shape and modulation index
- Data-rate programmable from 3 Mbits/s to 62.5 kbits/s (4 Mbits/s with 4-FSK)
- IEEE 802.15.4 chip encoding & decoding
- Manchester encoding
- Data whitening
- Packet handling
- Automatic preamble and sync word insertion
- Automatic packet length handler
- Basic address check
- Automatic CRC calculation and verification with a programmable CRC polynomial
- Multi-frame support
- 2x128 bytes FIFO
- Bluetooth Low Energy Long Range
- SPI and AMBA APB interfaces

Combined with the 2 Mbits/s analog front-end, the RFFE is capable of addressing Bluetooth Low Energy and Zigbee modulations.

RFFE is clocked from the 48 MHz crystal oscillator and is powered and enabled through registers ACS_VDDRF_CTRL, SYSCTRL_RF_POWER_CFG, and SYSCTRL_RF_ACCESS_CFG.

The power amplifier (PA) of RFFE is powered through VDDRF or VDDPA, configured by the user application for desired output power. For power outputs higher than 2 dBm, VDDPA needs to be enabled and connected to the PA (power amplifier) supply; otherwise VDDPA can be disabled and VDDRF supplies PA.