### BB_RWBLEBCONF

Bit Field | Read/Write | Field Name | Description
--- | --- | --- | ---
31 | R | DMMODE | RW-BLE core dual mode
29 | R | WLANCOEX | WLAN coexistence mechanism
28 | R | CORRELATOR | Correlator present
27 | R | USERXLR | Long range Rx present
26 | R | USETXLR | Long range Tx present
24 | R | USEISO | Support of isochronous channels
22:16 | R | RFIF | Support of the RF front-end
15 | R | USEDBG | Diagnostic port
14 | R | DECIPHER | AES deciphering present
13:8 | R | CLK_SEL | Operating frequency (in MHz)
7 | R | INTMODE | Interruption mode
6 | R | BUSTYPE | Processor bus type
4:0 | R | ADD_WIDTH | Value of the RW_BLE_ADDRESS_WIDTH parameter concerted into binary

Bit Field | Field Name | Value Symbol | Value Description | Hex Value
--- | --- | --- | --- | ---
31 | DMMODE | DMMODE_0 | RW-BLE core is used as a standalone BLE device | 0x0*
|  | DMMODE_1 | RW-BLE core is used in a dual mode device | 0x1
29 | WLANCOEX | COEX_0 | WLAN coexistence mechanism not present | 0x0
|  | COEX_1 | WLAN coexistence mechanism present | 0x1*
28 | CORRELATOR | CORRELATOR_0 | Correlator logic is not present | 0x0*
|  | CORRELATOR_1 | Correlator logic is present | 0x1
27 | USERXLR | USERXLR_0 | Long Range receive bit-stream logic is not present | 0x0*
|  | USERXLR_1 | Long Range receive bit-stream logic is present | 0x1
26 | USETXLR | USETXLR_0 | Long Range transmit bit-stream logic is not present | 0x0
|  | USETXLR_1 | Long Range transmit bit-stream logic is present | 0x1*
24 | USEISO | USEISO_0 | Isochronous channel feature not supported | 0x0*
|  | USEISO_1 | Isochronous channel feature supported | 0x1
22:16 | RFIF | RFIF_RIPPLE | Ripple and Thesis RF | 0x1
|  | RFIF_EXT | External radio controller support | 0x2
|  | RFIFCALYPSO | Calypso radio | 0x4
|  | RFIF_ICYTRX_V2 | IcyTRx version 2 radio | 0x8*
|  | RFIF_BTIPT | BTIPT radio | 0x10
|  | RFIF_AURA_SEMI | Aura semi 50xx radio | 0x20
|  | RFIF_RESERVED | Reserved | 0x40
15 | USEDBG | USEDBG_0 | WLAN coexistence mechanism present | 0x0
|  | USEDBG_1 | Diagnostic port instantiated | 0x1*
14 | DECIPHER | DECIPHER_0 | AES deciphering not present | 0x0*
|  | DECIPHER_1 | AES deciphering present | 0x1
13:8 | CLK_SEL | CLK_SEL_8 | Default value is 8MHz | 0x8*
7 | INTMODE | INTMODE_0 | Interrupts are edge level generated, i.e. pulse | 0x0*
|  | INTMODE_1 | Interrupts are trigger level generated, i.e. stays active at 1 till acknowledgement | 0x1
6 | BUSTYPE | BUSTYPE_0 | Processor bus type: AHB bus | 0x0
|  | BUSTYPE_1 | Processor bus type: XBAR bus | 0x1*
4:0 | ADD_WIDTH | ADD_WIDTH_14 | EM size is 16kB | 0xE*