### DMA_CFG0

Bit Field | Read/Write | Field Name | Description
--- | --- | --- | ---
31 | RW | COMPLETE_INT_ENABLE | Raise an interrupt when the DMA transfer completes
30 | RW | CNT_INT_ENABLE | Raise an interrupt when the DMA transfer reaches the counter value
29 | RW | DEST_ADDR_LSB_TOGGLE | Enable an address LSB toggling for the destination
28 | RW | SRC_ADDR_LSB_TOGGLE | Enable an address LSB toggling for the source
27:24 | RW | DEST_ADDR_STEP | Configure whether the destination address increments/decrements in terms of destination word size
23:20 | RW | SRC_ADDR_STEP | Configure whether the source address increments/decrements in terms of source word size
19:14 | RW | SRC_DEST_WORD_SIZE | Select the source and destination word sizes for the transfer
13:10 | RW | DEST_SELECT | Select the request line for the destination
8:5 | RW | SRC_SELECT | Select the request line for the source
3:2 | RW | CHANNEL_PRIORITY | Select the priority level for this channel
1 | RW | SRC_DEST_TRANS_LENGTH_SEL | Selects whether the transfer length counter depends on either the source word counts or the destination word count
0 | RW | BYTE_ORDER | Select the byte ordering of the DMA channel

Bit Field | Field Name | Value Symbol | Value Description | Hex Value
--- | --- | --- | --- | ---
31 | COMPLETE_INT_ENABLE | DMA_COMPLETE_INT_DISABLE | Disable completion interrupts for DMA channel | 0x0*
|  | DMA_COMPLETE_INT_ENABLE | Enable completion interrupts for DMA channel | 0x1
30 | CNT_INT_ENABLE | DMA_CNT_INT_DISABLE | Disable counter interrupts for DMA channel | 0x0*
|  | DMA_CNT_INT_ENABLE | Enable counter interrupts for DMA channel | 0x1
29 | DEST_ADDR_LSB_TOGGLE | DMA_DEST_ADDR_LSB_TOGGLE_DISABLE | No toggling on the destination address LSB | 0x0*
|  | DMA_DEST_ADDR_LSB_TOGGLE_ENABLE | Toggle the destination address LSB | 0x1
28 | SRC_ADDR_LSB_TOGGLE | DMA_SRC_ADDR_LSB_TOGGLE_DISABLE | No toggling on the source address LSB | 0x0*
|  | DMA_SRC_ADDR_LSB_TOGGLE_ENABLE | Toggle the source address LSB | 0x1
27:24 | DEST_ADDR_STEP | DMA_DEST_ADDR_STATIC | Do not increment the destination address used by DMA channel | 0x0*
|  | DMA_DEST_ADDR_INCR_1 | Set the step size of DMA channel destination address to 1 | 0x1
|  | DMA_DEST_ADDR_INCR_2 | Set the step size of DMA channel destination address to 2 | 0x2
|  | DMA_DEST_ADDR_INCR_3 | Set the step size of DMA channel destination address to 3 | 0x3
|  | DMA_DEST_ADDR_INCR_4 | Set the step size of DMA channel destination address to 4 | 0x4
|  | DMA_DEST_ADDR_INCR_5 | Set the step size of DMA channel destination address to 5 | 0x5
|  | DMA_DEST_ADDR_INCR_6 | Set the step size of DMA channel destination address to 6 | 0x6
|  | DMA_DEST_ADDR_INCR_7 | Set the step size of DMA channel destination address to 7 | 0x7
|  | DMA_DEST_ADDR_DECR_8 | Set the step size of DMA channel destination address to minus 8 | 0x8
|  | DMA_DEST_ADDR_DECR_7 | Set the step size of DMA channel destination address to minus 7 | 0x9
|  | DMA_DEST_ADDR_DECR_6 | Set the step size of DMA channel destination address to minus 6 | 0xA
|  | DMA_DEST_ADDR_DECR_5 | Set the step size of DMA channel destination address to minus 5 | 0xB
|  | DMA_DEST_ADDR_DECR_4 | Set the step size of DMA channel destination address to minus 4 | 0xC
|  | DMA_DEST_ADDR_DECR_3 | Set the step size of DMA channel destination address to minus 3 | 0xD
|  | DMA_DEST_ADDR_DECR_2 | Set the step size of DMA channel destination address to minus 2 | 0xE
|  | DMA_DEST_ADDR_DECR_1 | Set the step size of DMA channel destination address to minus 1 | 0xF
23:20 | SRC_ADDR_STEP | DMA_SRC_ADDR_STATIC | Do not increment the source address used by DMA channel | 0x0*
|  | DMA_SRC_ADDR_INCR_1 | Set the step size of DMA channel source address to 1 | 0x1
|  | DMA_SRC_ADDR_INCR_2 | Set the step size of DMA channel source address to 2 | 0x2
|  | DMA_SRC_ADDR_INCR_3 | Set the step size of DMA channel source address to 3 | 0x3
|  | DMA_SRC_ADDR_INCR_4 | Set the step size of DMA channel source address to 4 | 0x4
|  | DMA_SRC_ADDR_INCR_5 | Set the step size of DMA channel source address to 5 | 0x5
|  | DMA_SRC_ADDR_INCR_6 | Set the step size of DMA channel source address to 6 | 0x6
|  | DMA_SRC_ADDR_INCR_7 | Set the step size of DMA channel source address to 7 | 0x7
|  | DMA_SRC_ADDR_DECR_8 | Set the step size of DMA channel source address to minus 8 | 0x8
|  | DMA_SRC_ADDR_DECR_7 | Set the step size of DMA channel source address to minus 7 | 0x9
|  | DMA_SRC_ADDR_DECR_6 | Set the step size of DMA channel source address to minus 6 | 0xA
|  | DMA_SRC_ADDR_DECR_5 | Set the step size of DMA channel source address to minus 5 | 0xB
|  | DMA_SRC_ADDR_DECR_4 | Set the step size of DMA channel source address to minus 4 | 0xC
|  | DMA_SRC_ADDR_DECR_3 | Set the step size of DMA channel source address to minus 3 | 0xD
|  | DMA_SRC_ADDR_DECR_2 | Set the step size of DMA channel source address to minus 2 | 0xE
|  | DMA_SRC_ADDR_DECR_1 | Set the step size of DMA channel source address to minus 1 | 0xF
19:14 | SRC_DEST_WORD_SIZE | WORD_SIZE_32BITS_TO_32BITS | source data uses 32-bit word and destination data uses 32-bit word | 0x0*
|  | WORD_SIZE_32BITS_TO_4BITS | source data uses 32-bit word and destination data uses 4-bit word | 0x1
|  | WORD_SIZE_32BITS_TO_8BITS | source data uses 32-bit word and destination data uses 8-bit word | 0x2
|  | WORD_SIZE_32BITS_TO_16BITS | source data uses 32-bit word and destination data uses 16-bit word | 0x4
|  | WORD_SIZE_4BITS_TO_32BITS | source data uses 4-bit word and destination data uses 32-bit word | 0x8
|  | WORD_SIZE_4BITS_TO_4BITS | source data uses 4-bit word and destination data uses 4-bit word | 0x9
|  | WORD_SIZE_4BITS_TO_8BITS | source data uses 4-bit word and destination data uses 8-bit word | 0xA
|  | WORD_SIZE_4BITS_TO_16BITS | source data uses 4-bit word and destination data uses 16-bit word | 0xC
|  | WORD_SIZE_8BITS_TO_32BITS | source data uses 8-bit word and destination data uses 32-bit word | 0x10
|  | WORD_SIZE_8BITS_TO_4BITS | source data uses 8-bit word and destination data uses 4-bit word | 0x11
|  | WORD_SIZE_8BITS_TO_8BITS | source data uses 8-bit word and destination data uses 8-bit word | 0x12
|  | WORD_SIZE_8BITS_TO_16BITS | source data uses 8-bit word and destination data uses 16-bit word | 0x14
|  | WORD_SIZE_16BITS_TO_32BITS | source data uses 16-bit word and destination data uses 32-bit word | 0x20
|  | WORD_SIZE_16BITS_TO_4BITS | source data uses 16-bit word and destination data uses 4-bit word | 0x21
|  | WORD_SIZE_16BITS_TO_8BITS | source data uses 16-bit word and destination data uses 8-bit word | 0x22
|  | WORD_SIZE_16BITS_TO_16BITS | source data uses 16-bit word and destination data uses 16-bit word | 0x24
13:10 | DEST_SELECT | DMA_DEST_ALWAYS_ON | Data writes are always triggered | 0x0*
|  | DMA_DEST_SPI0 | Data writes are triggered by the SPI0 request line | 0x1
|  | DMA_DEST_SPI1 | Data writes are triggered by the SPI1 request line | 0x2
|  | DMA_DEST_I2C0 | Data writes are triggered by the I2C0 request line | 0x3
|  | DMA_DEST_I2C1 | Data writes are triggered by the I2C1 request line | 0x4
|  | DMA_DEST_UART0 | Data writes are triggered by the UART0 request line | 0x5
|  | DMA_DEST_PCM0 | Data writes are triggered by the PCM0 request line | 0x6
|  | DMA_DEST_TOF | Data writes are triggered by the TOF request line | 0x7
|  | DMA_DEST_NOT_USED_8 | Data writes are triggered by the DEST_NOT_USED_8 request line | 0x8
|  | DMA_DEST_NOT_USED_9 | Data writes are triggered by the DEST_NOT_USED_9 request line | 0x9
|  | DMA_DEST_NOT_USED_10 | Data writes are triggered by the DEST_NOT_USED_10 request line | 0xA
|  | DMA_DEST_NOT_USED_11 | Data writes are triggered by the DEST_NOT_USED_11 request line | 0xB
|  | DMA_DEST_NOT_USED_12 | Data writes are triggered by the DEST_NOT_USED_12 request line | 0xC
|  | DMA_DEST_NOT_USED_13 | Data writes are triggered by the DEST_NOT_USED_13 request line | 0xD
|  | DMA_DEST_NOT_USED_14 | Data writes are triggered by the DEST_NOT_USED_14 request line | 0xE
|  | DMA_DEST_NOT_USED_15 | Data writes are triggered by the DEST_NOT_USED_15 request line | 0xF
8:5 | SRC_SELECT | DMA_SRC_ALWAYS_ON | Data reads are always triggered | 0x0*
|  | DMA_SRC_SPI0 | Data reads are triggered by the SPI0 request line | 0x1
|  | DMA_SRC_SPI1 | Data reads are triggered by the SPI1 request line | 0x2
|  | DMA_SRC_I2C0 | Data reads are triggered by the I2C0 request line | 0x3
|  | DMA_SRC_I2C1 | Data reads are triggered by the I2C1 request line | 0x4
|  | DMA_SRC_UART0 | Data reads are triggered by the UART0 request line | 0x5
|  | DMA_SRC_PCM0 | Data reads are triggered by the PCM0 request line | 0x6
|  | DMA_SRC_TOF | Data reads are triggered by the TOF request line | 0x7
|  | DMA_SRC_RF_IQ_READY | Data reads are triggered by the RF_IQ_READY request line | 0x8
|  | DMA_SRC_RF_PHASE_ADC_READY | Data reads are triggered by the RF_PHASE_ADC_READY request line | 0x9
|  | DMA_SRC_NOT_USED_10 | Data reads are triggered by the SRC_NOT_USED_10 request line | 0xA
|  | DMA_SRC_NOT_USED_11 | Data reads are triggered by the SRC_NOT_USED_11 request line | 0xB
|  | DMA_SRC_NOT_USED_12 | Data reads are triggered by the SRC_NOT_USED_12 request line | 0xC
|  | DMA_SRC_NOT_USED_13 | Data reads are triggered by the SRC_NOT_USED_13 request line | 0xD
|  | DMA_SRC_NOT_USED_14 | Data reads are triggered by the SRC_NOT_USED_14 request line | 0xE
|  | DMA_SRC_NOT_USED_15 | Data reads are triggered by the SRC_NOT_USED_15 request line | 0xF
3:2 | CHANNEL_PRIORITY | DMA_PRIORITY_0 | Set the priority of DMA channel to 0 (Lowest) | 0x0*
|  | DMA_PRIORITY_1 | Set the priority of DMA channel to 1 | 0x1
|  | DMA_PRIORITY_2 | Set the priority of DMA channel to 2 | 0x2
|  | DMA_PRIORITY_3 | Set the priority of DMA channel to 3 (highest) | 0x3
1 | SRC_DEST_TRANS_LENGTH_SEL | DEST_TRANS_LENGTH_SEL | Transfer length counter depends on the destination word count | 0x0*
|  | SRC_TRANS_LENGTH_SEL | Transfer length counter depends on the source word count | 0x1
0 | BYTE_ORDER | DMA_LITTLE_ENDIAN | DMA channel uses little endian mode | 0x0*
|  | DMA_BIG_ENDIAN | DMA channel uses big endian mode | 0x1