# Introduction

The Arm Cortex-M33 processor implements the Armv8-M architecture. It has the following main features:

- Thumb-2 (ISA) subset consisting of all base Thumb-2 instructions, both 16-bit and 32-bit
- Harvard processor architecture enabling simultaneous instruction fetches with data load or store
- Three-stage pipeline
- Single cycle 32-bit multiply
- Hardware divide
- Thumb and debug states
- Handler and thread modes
- Low latency interrupt subroutine (ISR) entry and exit
- Processor state saving and restoration, with no instruction fetch overhead; the exception vector is fetched from memory in parallel with the state saving, enabling faster ISR entry
- Support for late-arriving interrupts
- Tightly coupled interface to interrupt controller, enabling efficient processing of late-arriving interrupts
- Tail-chaining of interrupts, enabling back-to-back interrupt processing without the overhead of state saving and restoration between interrupts
- Interruptible-continued LDM/STM, and PUSH/POP
- Includes floating point, DSP extensions
- Includes security extension, and secure protected memory regions (MPU) including the Secure Attribution Unit (SAU)
- Armv6 style BE8/LE support
- Armv6 unaligned
- Registers:
  - 13 general-purpose 32-bit registers
  - Link Register (LR)
  - Program Counter (PC)
  - Program Status Register (xPSR)
  - Two banked SP registers

Following a power-on reset (POR), the system starts executing the Boot ROM on the Arm Cortex-M33 processor, and uses this ROM application to initialize the system, and validate a system application is both likely to be valid and is secured by the Root of Trust. For more information about the Boot ROM code, see the RSL15 Firmware Reference. For more information on the security system, see Arm TrustZone CryptoCell-312 Security IP.

To reduce the current consumption from fetching instructions, the Arm Cortex-M33 processor is supported by a 32-instruction loop cache that can be used to cover a continuous block of reads. To enable this cache, set the CSS_LOOP_CACHE_ENABLE bit from the SYSCTRL_CM33_LOOP_CACHE_CFG register.