# Watchdog Timer

The watchdog timer is a safety mechanism that resets a system that has malfunctioned. This safety system uses a timer that must be periodically renewed by writing WATCHDOG_REFRESH to the WATCHDOG_CTRL register before it reaches its timeout value (WATCHDOG_CTRL_TIMEOUT). The system assumes that the application’s failure to acknowledge this timer before it reaches WATCHDOG_CTRL_TIMEOUT twice indicates that the system is malfunctioning and must be reset. The timer value for the watchdog timer is not visible to the core.

IMPORTANT: The watchdog counter is cleared when the DEBUG_HALT_CTRL_C_DEBUGEN bit in the DEBUG_HALT_CTRL register is set. This prevents watchdog timeouts during code development for the RSL15. The watchdog timer is disabled as long as the debug port is powered up.

The watchdog timer runs on a prescaled clock that has been derived from the SLOWCLK using a fixed division of 1024. This clock is used to control the value in the watchdog’s 13-bit counter.

When the watchdog timer is refreshed, a configurable number of bits in the 13-bit counter are reset and the prescaling counter is reset. The watchdog times out when it reaches the value contained by the WATCHDOG_CTRL_TIMEOUT bit field in the WATCHDOG_CTRL register. The number of cycles that must elapse between refresh events to trigger a watchdog timeout event is defined by the following equation:

The watchdog has an associated warning interrupt that is pended if the watchdog timer times out. When this interrupt is pended, the watchdog timeout restarts, and if the watchdog timer still has not been reset and a second watchdog timeout occurs, a hard reset follows. For more information about resets, see Resets.

NOTE: In standby power mode (see Power Modes) the watchdog timer is not clocked. Despite this status, to prevent resets when returning from standby mode to run mode, we recommend refreshing the watchdog timer immediately before transitioning to standby mode.

IMPORTANT: For best practices in error, fault, and watchdog interrupt handling see Diagnostic Strategies from the RSL15 Developer's Guide.

For registers, see Watchdog Timer Registers.