# Overview

SYSCLK can be generated from one of five different sources for maximum flexibility. Available sources for SYSCLK include:

1. The internal startup system RC clock (discussed in RC Oscillator)
2. The RF clock provided by the system crystal clock (discussed in 48 MHz Crystal Oscillator)
3. STANDBYCLK
4. The SWCLK pad from the SWJ-DP (discussed in Debug Port Clock)
5. EXTCLK, provided at a selected GPIO

For more information about configuring SYSCLK, see System Clock (SYSCLK).

Similarly, the STANDBYCLK can be generated from two different sources, including:

1. The internal standby RC oscillator (discussed in Standby RC Oscillator)
2. The 32 kHz crystal oscillator (discussed in Section 32 kHz Crystal Oscillator)

For more information about configuring STANDBYCLK, see Standby Clock (STANDBYCLK)).

A top-level clock diagram showing the clock generation and distribution of clocks within the RSL15 system is provided in the "Overview" figure.