# RFFE Interface

## RFFE PowerUp

The RF front-end interface is controlled by two blocks/register groups that respectively configure the components external to the RFFE, and configure and access the components that are internal to the RFFE. The first register group is part of the SYSCTRL registers that are used to power and access RFFE, and to control or configure the interface to RFFE. Without having RFFE enabled they are accessible, and are located outside of the RFFE block. The second group of registers are located inside the RFFE block, and are accessible only if the SYSCTRL_RF_POWER_CFG and SYSCTRL_RF_ACCESS_CFG registers are configured for RF power and access.

The following steps are required to power up the RFFE:

1. Enable power to the RFFE interface, by enabling the VDDRF supply or ensuring that it has been previously enabled.
2. Disable the VDDPA if it is not needed, connecting VDDPA to VDDRF.
3. Enable the RFFE itself.
4. Enable the 48 MHz crystal oscillator needed by the RFFE.
5. Route interrupts from the RFFE to the system.

To enable the VDDRF and disable VDDPA if it is not needed, a user application needs to perform the following steps:

1. Enable the VDDRF supply, by setting the ACS_VDDRF_CTRL_VDDRF_ENABLE bit in the ACS_VDDRF_CTRL register, making no changes to the trimming settings.
2. Wait until the ACS_VDDRF_CTRL_VDDRF_READY bit from the ACS_VDDRF_CTRL register is set to VDDRF_READY, indicating the VDDRF supply has powered up.
3. Connect VDDPA to VDDRF, by disabling the VDDPA regulator. This is accomplished by clearing the ACS_VDDPA_CTRL_VDDPA_ENABLE bit in the ACS_VDDPA_CTRL register to VDDPA_DISABLE.

To enable RFFE, the following sequence needs to be applied:

1. Set the SYSCTRL_RF_POWER_CFG_RF_STARTUP field of register SYSCTRL_RF_POWER_CFG.
2. Set the SYSCTRL_RF_POWER_CFG_RF_ENABLE bit of the same register (keeping the startup bit set), to enable the power switch.
3. Set the SYSCTRL_RF_ACCESS_CFG_RF_ACCESS bit in register SYSCTRL_RF_ACCESS_CFG, to grant access.

A power-up duration of 1.3 µs is automatically enforced using wait states on the internal bus when powering up the RF block. See RF Front-End Registers for more details.

NOTE: To disable the RFFE, follow the enabling steps in reverse order by disabling access first and then disabling the power switch.

To enable the 48 MHz XTAL oscillator to provide the clock to RFFE, perform the following steps:

1. Set the RF_XTAL_CTRL_DISABLE_OSCILLATOR and RF_XTAL_CTRL_XTAL_CTRL_REG_VALUE_SEL_INTERNAL bits from the RF_XTAL_CTRL register, to start the 48 MHz crystal oscillator.
2. Set the RF0_REG33_CK_DIV_1_6_CK_DIV_1_6 field in the RF0_REG33 register to the desired prescale value for enabling the 48 MHz crystal oscillator divider.
3. Pause the code until the 48 MHz crystal oscillator is started, using value of the RF0_ANALOG_INFO_ANALOG_INFO_CLK_DIG_READY bit in the RF0_ANALOG_INFO register a Ready signal for the clock.

To enable the routing of interrupts from the RFFE baseband to the system, the SYSCTRL_RF_ACCESS_CFG_RF_IRQ_ACCESS field of register SYSCTRL_RF_ACCESS_CFG needs to be enabled. This configuration allows an application to enable and use the internal configuration of the IRQs of the RFFE as well, as described later in this chapter.

## VDDPA Dynamic Control

VDDPA is required to be enabled for output powers higher than 2 dBm. It can be enabled and used for lower output powers as well, but this causes more power consumption. To mitigate the affect of power amplifier activation during signal transmission and help to pass band edge regulatory tests, there is a hardware mechanism called VDDPA dynamic control, which can be enabled by setting the SYSCTRL_VDDPA_CFG0_DYNAMIC_CTRL bit of the SYSCTRL_VDDPA_CFG0 register. The purpose of the mechanism is twofold:

1. Dynamically enable/disable the VDDPA regulator during (respectively) TX and RX operations, to minimize the power consumption. The mechanism automatically controls the enabling/switching of the VDDPA regulator when the ACS_VDDPA_CTRL_VDDPA_ENABLE bit in the ACS_VDDPA_CTRL register is reset, and the ACS_VDDPA_CTRL_VDDPA_SW_CTRL bit in the same register is set.
2. Mitigate possible out-of-band issues by applying a progressive voltage ramp-up/-down on the VDDPA regulator supplying the RF front-end PA. The mechanism dynamically controls the VDDPA voltage in the range specified by the ACS_VDDPA_CTRL_VDDPA_INITIAL_VTRIM and ACS_VDDPA_CTRL_VDDPA VTRIM fields of the ACS_VDDPA_CTRL register.

The different voltage ramp-up/-down steps need to be properly synchronized with the RFFE FSM TX operations as shown in the "Timing Relationship Between VDDPA Dynamic Control Mechanism and RFFE Operations" figure. All the times and delays hereafter are specified in system clock cycles. Note that when VDDRF is used to power PA, there is no need to enable this mechanism and it has no effect.

Figure: Timing Relationship Between VDDPA Dynamic Control Mechanism and RFFE Operations

1. Apply the voltage ramp-up in the continuity of the internal RF front-end PA power ramp-up, but before the transmission of the first bit over the air:
   1. The VDDPA regulator is automatically enabled when the FSM starts in TX mode.
   2. The SW_CTRL switches the PA supply source from VDDRF to VDDPA after the delay specified in the SYSCTRL_VDDPA_CFG0_SW_CTRL_DELAY field of the SYSCTRL_VDDPA_CFG0 register. The VDDPA regulator is trimmed at the value specified in the ACS_VDDPA_CTRL_INITIAL_VTRIM field of the ACS_VDDPA_CTRL register.
   3. The voltage ramp-up starts after the delay specified in the SYSCTRL_VDDPA_CFG0_RAMPUP_DELAY field of the SYSCTRL_VDDPA_CFG0 register. The voltage ramp-up stops when VDDPA reaches the VTRIM trim target specified in the ACS_VDDPA_CTRL_INITIAL_VTRIM field of the ACS_VDDPA_CTRL register.
   4. The number of ramp-up voltage steps is configured in the SYSCTRL_VDDPA_CFG1_RAMPUP_STEP field of the SYSCTRL_VDDPA_CFG1 register, while the duration of each step is defined in the SYSCTRL_VDDPA_CFG1_RAMPUP_STEP_TIME field of the same register. Consequently, the total ramp-up time is given by SYSCTRL_VDDPA_CFG1_RAMPUP_STEP times SYSCTRL_VDDPA_CFG1_RAMPUP_STEP_TIME.
2. Apply the voltage ramp-down when TX stops, but before the start of the internal RF front-end PA power ramp-down:
   1. The voltage ramp-down automatically starts when the FSM stops. The voltage ramp-down stops when VDDPA reaches the trim target value specified in the ACS_VDDPA_CTRL_INITIAL_VTRIM field of the ACS_VDDPA_CTRL register.
   2. The amount of ramp-down voltage steps is configured in the SYSCTRL_VDDPA_CFG1_RAMDOWN_STEP field of the SYSCTRL_VDDPA_CFG1 register, while the duration of each step is defined in the SYSCTRL_VDDPA_CFG1_RAMPDOWN_STEP_TIME field of the same register. Consequently, the total ramp-down time is given by SYSCTRL_VDDPA_CFG1_RAMPDOWN_STEP times SYSCTRL_VDDPA_CFG1_RAMPDOWN_STEP_TIME.
   3. The VDDPA regulator is disabled once the ramp-down is over and after the delay specified in the SYSCTRL_VDDPA_CFG0_DISABLE_DELAY field of the SYSCTRL_VDDPA_CFG0 register. The PA supply source is automatically switched from VDDPA to VDDRF one cycle later.
3. The initial VDDPA voltage (given by the ACS_VDDPA_CTRL_INITIAL_VTRIM field of the ACS_VDDPA_CTRL register) needs to be as close as possible to VDDRF. This ensures voltage continuity when switching the PA supply source from VDDPA to VDDRF and vice versa.
4. The dynamic regulator enabling/disabling can be bypassed by setting the ACS_VDDPA_CTRL_VDDPA_ENABLE bit in the ACS_VDDPA_CTRL register, and resetting the ACS_VDDPA_CTRL_VDDPA_SW_CTRL in the same register. In this case, the regulator is kept always on while the dynamic voltage control remains active.
5. We recommend that you enable/disable the VDDPA dynamic control only when the radio is idle (no TX or RX), to avoid unexpected behavior of the VDDPA voltage.
6. The actual status of the VDDPA regulator (trimming, enable and switch) can be read in the SYSCTRL_VDDPA_CFG0 register.

## RFFE Data Steaming

The phase ADC has a resolution of 4 bits, and provides the Arctan(Q/I) and RSSI detectors. The RSSI detector outputs a 30-bit thermometric code that is coded as a 5-bit value output in the RFFE modem. The received radio signals after down-conversion to the IF band is sampled thorough the phase ADC and the RSSI detector. While this information is internally passed to the demodulator of the RFFE, it is possible that the information is instead routed to the RFFE interface for access by system. There are two types of data that can be routed and streamed to the Arm Cortex-M33 processor or the DMA:

- RAW data: the phase ADC has a resolution of 4 bits, and it provides the Arctan(Q/I) and RSSI detector output that is a 30-bit thermometric code, coded as a 5-bit value output in the RFFE modem. Since the AGC algorithm changes different attenuation stages during signal reception to keep the signal amplitude in the working dynamic range of the receiver, the final RSSI output is affected by the total attenuation level. To know the actual signal level of the input signal, the AGC attenuation level needs to be taken into consideration. For this purpose, the phase ADC data, RSSI data, and corresponding AGC attenuation level (4 bits) can be configured in such a way that these data samples that are available at RFFE interface level can be written to some registers to be accessed by the Arm Cortex-M33 processor or the DMA.

- I/Q data: It is possible that I and Q channel data can be sampled periodically after matched filtering, and placed into the RFFE interface.

### 7.2.6.3.1 Phase ADC and RSSI data streaming

Phase ADC and RSSI streaming, when required, needs to be enabled in SYSCTRL and RFFE. This is done both through setting the RF_DATA_STREAMING_DATA_STREAMING_DMA_EN_BUS field of the RF_DATA_STREAMING register in the RFFE for streaming data to the interface, and by setting the bit SYSCTRL_RFIF_CTRL_PHASE_ADC_STREAMING of the SYSCTRL_RFIF_CTRL register for sampling the data on the core side. To help data processing in SW, some flags can be added to the streamed data when a packet is received. When the access word of a packet is detected, a flag can be added to all data after that moment, and when the RX reception signal goes down in the RFFE, another flag can be added to all data after that time, indicating the end of the packet. In the middle of a Bluetooth Low energy packet reception, CTE can be included, and if it is configured to stream data for the CTE period, another flag can be added to packed data related to CTE duration. The RF front-end starts or stops streaming data with the RX activity. The different flags are reset when the RX activity starts, and are set as soon as the corresponding event is detected (sync word, CTE mode or packet end). Two consecutive 16-bit phase ADC data items are temporarily stored into a 32-bit data buffer. The latter is updated when a new phase ADC data pair is available, at the rate of 4 MHz and 8 MHz for 1 Mbps and 2 Mbps data rates over the air (respectively). The 32-bit data is available at the RFFE interface as shown in the "Packed Data Format of Phase ADC, RSSI, and Related Flags at the RFFE Interface" figure where indexes 0 and 1 refer to the data at two consecutive time instants:

Figure: Packed Data Format of Phase ADC, RSSI, and Related Flags at the RFFE Interface

The phase ADC data-ready signal is set when new 32-bit data (i.e., two consecutive phase ADC data items) is available. Consequently, the last phase ADC data is lost if the amount of phase ADC data is an odd number. The system core clock needs to be at least four times faster than the 32-bit data rate (16 and 32 MHz for 1 and 2 Mbps Bluetooth Low Energy PHY rates). The sampled 32-bit data is mapped to several registers providing different data formatting (ADC here refers to phase ADC):

1. The SYSCTRL_RFIF_PHASE_ADC_FLAGS register provides the 32-bit data information of two consecutive phase ADC data with the flags.
2. The SYSCTRL_RFIF_PHASE_ADC register provides the 32-bit data information of two consecutive phase ADC data items without the flags.
3. The SYSCTRL_RFIF_PHASE_ADC_0 register provides a 32-bit byte-aligned version of the phase ADC data 0 and flags (ADC, AGC, RSSI and flags are stored in separate bytes).
4. The SYSCTRL_RFIF_PHASE_ADC_1 register provides a 32-bit byte-aligned version of the phase ADC data 1 and flags (ADC, AGC, RSSI and flags are stored in separate bytes).

The data-ready signal is used as a request source for the DMA to copy one item of data from the SYSCTRL_RFIF_PHASE_ADC_FLAGS or SYSCTRL_RFIF_PHASE_ADC registers, or two data items from the SYSCTRL_RFIF_PHASE_ADC_0 and SYSCTRL_RFIF_PHASE_ADC_1 registers.

A 16-bit counter is incremented by two when a data-ready rising edge is detected. The counter is reset to 0xFFFF by setting the SYSCTRL_RFIF_CTRL_COUNTER_CLEAR bit in the SYSCTRL_RFIF_CTRL register. The current counter state is mapped to the SYSCTRL_RFIF_COUNTER register. The counter state is stored in the following dedicated registers when the following events happens:

1. Stored in the SYSCTRL_RFIF_SYNC_WORD register when the sync word flag is set
2. Stored in the SYSCTRL_RFIF_CTE_START register when the CTE mode flag is set
3. Stored in the SYSCTRL_RFIF_PACKET_END register when the packet end flag is set

The LSB of the counter state stored in the above registers is reset if the event coincides with the phase ADC data 0. Each register is updated only once, when the first corresponding event is detected. Each register can be independently reset to 0xFFFF by setting the corresponding clear bit in the SYSCTRL_RFIF_CTRL register. It is the user application’s responsibility to clear those registers when enabling the phase ADC data streaming and before every new RX event.

For testing purpose, dummy deterministic phase ADC data is generated by enabling the RF_AGC_ADVANCED_DEBUG_FAKE_IQ_SAMPLES bit of the RF_AGC_ADVANCED RFFE register.

### I/Q data streaming

The I/Q data streaming is enabled by configuring the following two registers to enable this functionality in RFFE and RFIF:

- Setting the RF_DATA_STREAMING_DATA_STREAMING_EN_PERIODIC_SAMPLE_IQ bit of the RF_DATA_STREAMING register in the RFFE for streaming data to the interface
- Setting the SYSCTRL_RFIF_CTRL_IQ_STREAMING bit of the SYSCTRL_RFIF_CTRL register for sampling the data on the core side

The 16-bit I/Q data is the RF_IQFIFO_IQFIFO_IQ_DATA signal currently available at the RFFE interface, found in the RF_IQFIFO_IQFIFO_IQ_DATA field of the RF_IQFIFO register. The LSB byte is the I signal and the MSB byte is Q signal. I/Q data streaming is available in both CTE and non-CTE modes. The RF front-end starts streaming when the sync word is detected, and stops when the packet end is detected (in Bluetooth Low Energy mode) or when the RX activity stops (in packet handler mode). The behavior in CTE mode remains unchanged. The data-ready signal is set when a new 16-bit data item is available at the RFFE interface. For both 1 and 2 Mbps Bluetooth Low Energy PHY rates and in non-CTE mode, the IQ data rate is 4 MHz, and it is 250 Kbps, 500 KHz, or 1 MHz in CTE mode according to the CTE sampling rate (slot duration of CTE).

For testing purpose, dummy deterministic I/Q data is generated by enabling the RF_AGC_ADVANCED_DEBUG_FAKE_IQ_SAMPLES bit of the RF_AGC_ADVANCED RF front-end register.