# Debug Control Block

Address | Register Name | Register Write | Register Read | Default | Description
--- | --- | --- | --- | --- | ---
0xE000EDF0 | DEBUG_DHCSR | (31:16) DBGKEY | - | N/A | Debug key must be written to this field in order to write the rest of the register
|  | - | (26) S_RESART_S | 0x0 | Restart sticky status
|  | - | (25) S_RESET_ST | 0x0 | Core has been reset or is being rest. Bit is cleared on read.
|  | - | (24) S_RETIRE_ST | 0x0 | Retire sticky status
|  | - | (20) S_SDE | 0x0 | Secure debug enable. Indicates whether Secure invasive debug is allowed
|  | - | (19) S_LOCKUP | 0x0 | Indicates if core is in lockup state
|  | - | (18) S_SLEEP | 0x0 | Indicates if core is in sleep mode
|  | - | (17) S_HALT | 0x0 | Indicates is core is halted
|  | - | (16) S_REGRDY | 0x0 | Indicates register read/write operation is completed
|  | (5) C_SNAPSTALL | (5) C_SNAPSTALL | 0x0 | Set to break a stalled memory access
|  | (3) C_MASKINTS | (3) C_MASKINTS | 0x0 | Mask interrupts while stepping
|  | (2) C_STEP | (2) C_STEP | 0x0 | Single step the processor
|  | (1) C_HALT | (1) C_HALT | 0x0 | Halt the processor
|  | (0) C_DEBUGEN | (0) C_DEBUGEN | 0x1 | Enable halt mode debugging
0xE000EDF4 | DEBUG_DCRSR | (16) REGWNR | - | N/A | Indicates direction of register transfer
|  | (6:0) REGSEL | - | N/A | Indicates register to be accessed
0xE000EDF8 | DEBUG_DCRDR | (31:0) DEBUG_REGDATA | (31:0) DEBUG_REGDATA | 0x0 | Register read/write data for debugging
0xE000EDFC | DEBUG_DEMCR |  |  |  |
0xE000EE04 | DEBUG_DAUTHCTRL | - | (3) INTSPNIDEN | 0x0 | Internal Secure non-invasive debug enable
|  | - | (2) SPNIDENSEL | 0x0 | Secure non-invasive debug enable select
|  | - | (1) INTSPIDEN | 0x0 | Internal Secure invasive debug enable
|  | - | (0) SPIDENSEL | 0x0 | Secure invasive debug enable select
0xE000EE08 | DEBUG_DSCSR | (17) CDSKEY | - | N/A | CDS write-enable key
|  | (16) CDS | (16) CDS | 0x0 | Current domain secure
|  | (1) SBRSEL | (1) SBRSEL | 0x0 | Secure banked register select
|  | (0) SBRSELEN | (0) SBRSELEN | 0x0 | Secure banked register select enable