### ACS_VDDCP_CTRL

Bit Field | Read/Write | Field Name | Description
--- | --- | --- | ---
24 | R | READY | Supply ready
13 | RW | COMP_ENABLE | Force cp comparator enable
11:8 | RW | CPCLK_FREQ | Charge Pump clock frequency during power down modes
1:0 | RW | PTRIM | Output power trimming

Bit Field | Field Name | Value Symbol | Value Description | Hex Value
--- | --- | --- | --- | ---
24 | READY | VDDCP_NOT_READY | Charge pump voltage not ready | 0x0*
|  | VDDCP_READY | Charge pump voltage ready | 0x1
13 | COMP_ENABLE | VDDCP_COMP_AUTO | Comparator and resistive divider turned off when not required | 0x0
|  | VDDCP_COMP_ENABLED | Comparator and resistive divider turned on (retro-compatible) | 0x1*
11:8 | CPCLK_FREQ | VDDCP_CPCLK_32KHZ | CP clock = 32 kHz (WDG_SoC clock) | 0x0
|  | VDDCP_CPCLK_16KHZ | CP clock = 16 kHz | 0x1
|  | VDDCP_CPCLK_8KHZ | CP clock = 8 kHz | 0x2*
|  | VDDCP_CPCLK_4KHZ | CP clock = 4 kHz | 0x3
|  | VDDCP_CPCLK_2KHZ | CP clock = 2 kHz | 0x4
|  | VDDCP_CPCLK_1KHZ | CP clock = 1 kHz | 0x5
|  | VDDCP_CPCLK_0P5KHZ | CP clock = 512 Hz | 0x6
|  | VDDCP_CPCLK_0P25KHZ | CP clock = 256 Hz | 0x7
|  | VDDCP_CPCLK_0P12KHZ | CP clock = 128 Hz | 0x8
1:0 | PTRIM | VDDCP_PTRIM_4MA | CP max current to 4 mA | 0x0
|  | VDDCP_PTRIM_8MA | CP max current to 8 mA | 0x1
|  | VDDCP_PTRIM_12MA | CP max current to 12 mA | 0x2
|  | VDDCP_PTRIM_16MA | CP max current to 16 mA | 0x3*