/*******************************************************************************
 * ON Semiconductor                                                            *
 * NCV7383 Evaluation KIT                                                      *
 *                                                                             *
 * Cpu.c                                                                       *
 * S12XF512 CPU initialization                                                 *
 * Interrupts configuration                                                    *
 *                                                                             *
 * Created by: Filip Brtan                                                     *
 * Date: 30.07.2012                                                            *
 *******************************************************************************/

/* MODULE Cpu. */

/** S12X derivative information */ 
#include "mc9s12xf512.h"  

/** Common defines and macros */
#include <hidef.h>   

/** Variable types and common definitions */
#include "typedefs.h"   

/** XGATE definitions */
#include "xgate.h"

#pragma DATA_SEG DEFAULT
#pragma CODE_SEG DEFAULT

/* Global variables */
volatile byte CCR_reg;                 /* Current CCR reegister */

/*******************************************************************************
*
* brief    PLL initialization, Bus Clock @ 40MHz
* param    void
* return   void
*/
void Clock_Settings(void)
{    
    /*  System clock initialization */
    /* OSCCLK = 8MHz */
    
    /* CLKSEL: PLLSEL=0,PSTP=0,XCLKS=0,??=0,PLLWAI=0,??=0,RTIWAI=1,COPWAI=0 */
    CLKSEL = 0;              /* Select clock source from XTAL               */ 
    CLKSEL_PSTP = 0;         /* Oscilator is disabled in STOP mode          */ 
    PLLCTL_CME = 1;          /* Clock monitor is enabled.                   */
                             /* Slow or stopped clocks will cause a clock   */
                             /* monitor reset sequence or Self Clock Mode   */
    PLLCTL_PLLON = 0;        /* Disable the PLL                             */
    PLLCTL_PRE = 0;          /* RTI stops running during Pseudo Stop Mode   */
    PLLCTL_FSTWKP = 1;       /* Fast wake-up from full stop mode is enabled */
    PLLCTL_SCME = 1;         /* Self Clock Mode Enabled                     */
    CLKSEL_RTIWAI = 0;       /* RTI keeps running in Wait Mode              */
    CLKSEL_PLLWAI = 0;       /* PLL keeps running in Wait Mode              */
              
    /* Fref = OSCCLK/(REFDIV+1) = 8MHz/(0+1) = 8MHz -> REFFRQ= 0b10         */    
    REFDV_REFDIV = 0x00;     /* PLL divider register                        */ 
    REFDV_REFFRQ = 0b10;     /* Reference Clock Frequency Selection         */
    
    /* Fvco = 2*OSCCLK*(SYNR+1)/(REFDIV+1) = 2*8MHz* (4+1)/(0+1) = 80MHz    */
    /*                                     -> VCOFRQ = 0b01                 */        
    SYNR_SYNDIV = 0x04;      /* PLL synthesizer register                    */
    SYNR_VCOFRQ = 0b01;      /* VCO Clock Frequency Selection               */
    
    POSTDIV_POSTDIV = 0x00;  /* Post Divider Register                       */
    /* Fpll  = fvco  / (2*POSTDIV)                                          */
    /* 80MHz = 80MHz / (1)                                                  */                                                    
    /* If POSTDIV = 0x00 then fPLL is identical to fVCO (divide by one).    */    
    /* Fbus = fpll/2 = 80MHz/2 = 40MHz                                      */
                                                                          
    PLLCTL_PLLON = 1;        /* PLL enabled                                 */
    
    while(!CRGFLG_LOCK)      /* Wait until the PLL is within the desired tolerance of the target frequency */
                
    CLKSEL_PLLSEL = 1;       /* Select clock source from PLL                */      
}


/*******************************************************************************
*
* brief    FlexRay IPLL initialization @ 80MHz
* param    void
* return   void
*/
void IPLL_Startup(void)
{
    /* Fref = OSCCLK/(REFDIV+1) = 8MHz/1 = 8MHz -> REFFRQ = 0b10      */ 
    CGMREFDV_REFDIV = 0x00;    /* CGMIPLL Reference Divider Register  */
    CGMREFDV_REFFRQ = 0b10;    /* Reference Clock Frequency Selection */
    
    /* Fvco = 2*OSCCLK*(SYNR+1)/(REFDV+1) = 2*8MHz*(4+1)/1 = 80MHz -> VCOFRQ = 01b */
    CGMSYNR_SYNDIV = 0x04;         
    CGMSYNR_VCOFRQ = 0b01;

    CGMCTL_DIV2 = 0;     /* DIV2=0 -> IPLL = Fvco  */ 

    CGMCTL_PLLON = 1;    /* IPLL enabled */

    while(!CGMFLG_LOCK); /* Wait until the PLL is within the desired tolerance of the target frequency */
}

/*******************************************************************************
*
* brief    CPU, XGATE, memory and ports settings
* param    void
* return   void
*/
void Peripheral_Settings(void)
{  
  /*******************************************************************************/
  /* Common initialization of the CPU registers */
  /*******************************************************************************/
 
  /* Initialize the XGATE vector block and the XGVBR register */    
  XGVBR= (unsigned int)(void*__far)(XGATE_VectorTable - XGATE_VECTOR_OFFSET);    
  /* disable XGATE mode and interrupts */
  XGMCTL= 0x0000; 
  
  /* FlexRay module access all memory */
  RAMFRL = 0x00;
  RAMFRU = 0xFF;
  
  /* COP module configuration */
  /* COPCTL: WCOP=0, RSBCK=0, WRTMASK=0, ??=0, ??=0, CR2=0, CR1=0, CR0=0, */
  //COPCTL = 0x00;  /* COP disabled */ 

  /* MMCCTL1: TGMRAMON=0,??=0,EEEIFRON=0,PGMIFRON=0,RAMHM=0,EROMON=0,ROMHM=0,ROMON=1 */
  MMCCTL1 = 1;    /* Enables Flash in the memory map */  

  /* DIRECT: DP15=0,DP14=0,DP13=0,DP12=0,DP11=0,DP10=0,DP9=0,DP8=0 */                
  DIRECT = 0;     /* Default location for direct page */ 

  /* IVBR: IVB_ADDR=255 */             
  IVBR = 0xFF;    /* Default vector base address */    

  /* ECLKCTL: NECLK=1,NCLKX2=1,DIV16=0,EDIV4=0,EDIV3=0,EDIV2=0,EDIV1=0,EDIV0=0 */
  ECLKCTL = 0b11000000;   /* Disable free-running clock on the ECLK and ECLKX2 pin. */                                                  

  /*******************************************************************************/
  /* Voltage regulator settings*/
  /* High Temperature Control Register */
  VREGHTCL = 0x10;        
  /* Control Register VREGCTRL */
  VREGCTRL = 0x00;             
  
  /* Autonomous Periodical Interrupt Control Register */
  VREGAPICL_APIFE = 0;
  VREGAPICL_APICLK = 0;    
  // VREG_API external pin is not used as a clock output
  VREGAPICL_APIES = 0; // External Select Bit
  VREGAPICL_APIEA = 0; // External Access Enable Bit   
   
  // APICLK = 0 => Period = 2*(APIR[15:0] + 1) * 0.1 ms 
  // 10 ms = 2*(49 + 1) * 0.1ms
  // 49 = 0x0031    
  /*Autonomous Periodical Interrupt Rate High and Low Register */
  VREGAPIRH = 0x00;  
  VREGAPIRL = 0x31;
    
  
  VREGAPICL_APIE = 1;  
  VREGAPICL_APIFE = 0;  
    
  /*******************************************************************************/
  /* Ports configuration */
  /*******************************************************************************/
    
  /*** PORT AD ***/
  /* ATD Input Enable Register */
  ATDDIENH = 0x00;  
  ATDDIENL = 0x00;  /* Disable digital input buffer on PAD pins */           
  
  /* Port AD Data Register */
  PT0AD = 0b00000000;  /* PT0AD[15:8] */
  PT1AD = 0b00000000;  /* PT1AD[ 7:0] */    
  
  /* Port AD Pull Up Enable Register */
  /* AUX_AD13--+         */
  /* AUX_AD14-+|         */
  /*          ||         */
  /*          VV         */
  PER0AD = 0b00000000; /* PER0AD[15:8] */             
  PER1AD = 0b00000000; /* PER1AD[ 7:0] (Pull-up devices disabled) */           
  
  /* Port AD Data Direction Register (0-input / 1-output) */
  /* AUX_AD13--+         */
  /* AUX_AD14-+|         */
  /*          ||         */
  /*          VV         */
  DDR0AD = 0b00000000; /* DDR0AD[15:8] (0-input / 1-output)*/
  DDR1AD = 0b00000000; /* DDR1AD[ 7:0] (0-input / 1-output)*/
  
  /* Port AD Reduced Drive Register */
  RDR0AD = 0x00; /* RDR0AD[15:0] */
  RDR1AD = 0x00; /* RDR0AD[ 7:0] (Full drive strength enabled) */
  

  /* PORTx  Port x Data Register */;
  /* DDRx   Port x Data Direction Register (0-input / 1-output) */
  /*                        */
  /* UV_VIO----++----BGE_A  */
  /* UV_VCC---+||+---STBN_A */
  /* SD_VIO--+||||+--CSN_A  */
  /* SD_VCC-+||||||+-ERRN_A */
  /*        ||||||||        */
  /*        VVVVVVVV        */
  PORTA = 0b11111010;   /* Port A Data */
  DDRA  = 0b11111110;   /* Port A (0-input / 1-output) */ 
    
  /* CSN_B --------+     */
  /* SDO_B -------+|     */
  /*              ||     */
  /*        VVVVVVVV     */
  PORTB = 0b00000001;   /* Port B Data */
  DDRB  = 0b00000001;   /* Port B (0-input / 1-output) */ 
  
  PORTC = 0x00;         /* Port C */
  DDRC  = 0x00;         /* Not implemented */ 
  
  PORTD = 0b00000000;   /* Port D (NOT USED) */
  DDRD  = 0b00111111;   /* Port D as output */
  
  /* XIRQ ---------+     */
  /* IRQ ---------+|     */
  /* BGE_B ------+||     */
  /* STBN_B ----+|||     */
  /* SCK_B ----+||||     */
  /* MODA ----+|||||     */
  /* MODB ---+||||||     */
  /* XCLK --+|||||||     */
  /*        ||||||||     */
  /*        VVVVVVVV     */
  PORTE = 0b00000100;   /* Port E Data */
  DDRE  = 0b00011100;   /* Port E (0-input / 1-output) */ 
  
  PORTK = 0;            /* Port K */
  DDRK  = 0x00;         /* Not implemented */
  
  /* Pull-up Control Register for ports A, B, C, D, E, K.  */
  /*        KB-EDCBA */
  PUCR  = 0b00000000; 
   
  /* Reduced drive on ports A, B, C, D, E, K. */   
  /*        K--EDCBA */     
  RDRIV = 0b11111110; /* Reduced drive selected */
  
  

  /* PTx Port x Data Register */ 
  /* DDRx Port x Data Direction Register (0-input / 1-output) */ 
  
  /* RXD_A --------+     */
  /* TXD_A -------+|     */
  /* TXEN_A -----+||     */
  /*       -----+|||     */
  /* RXD_B ----+||||     */
  /* TXD_B ---+|||||     */
  /* TXEN_B -+||||||     */
  /*       -+|||||||     */
  /*        ||||||||     */
  /*        VVVVVVVV     */
  PTH  =  0b01110111;  /* Port H */ 
  DDRH =  0b11101110;  /* Port H (0-input / 1-output)*/ 
  
  /* FR CC STB1..4 outputs */
  /*      ----------0     */
  /*      ---------1|     */
  /*      --------2||     */
  /* STB0 -------3|||     */
  /* STB1 ------4||||     */
  /* STB2 -----5|||||     */
  /* STB3 ----6||||||     */
  /* ERRN_B -7|||||||     */
  /*         ||||||||     */
  /*         VVVVVVVV     */ 
  PTJ  =   0b00000000;  /* Port J */ 
  DDRJ =   0b01111111;  /* Port J (0-input / 1-output) */ 
  
  /* CAN bus driver signals (CANRX as input) */
  
  /* RXCAN --------0     */
  /* TXCAN -------1|     */
  /* STBCAN -----2||     */
  /*       -----3|||     */
  /* SDO_A ----4||||     */
  /*       ---5|||||     */
  /* SCK_A --6||||||     */
  /*       -7|||||||     */
  /*        ||||||||     */
  /*        VVVVVVVV     */ 
  PTM  =  0b00000111;  /* Port M */
  DDRM =  0b11101110;  /* Port M (0-input / 1-output)*/ 
  
  /* LED Outputs */
  PTP  = 0b11111110;  /* Port P */
  DDRP = 0b11111111;  /* Port P (0-input / 1-output)*/ 
  
  /* UART0 pins and Aux outputs  */
  /* RXD0 ---------0     */
  /* TXD0 --------1|     */
  /* RXD1 -------2||     */
  /* TXD1 ------3|||     */
  /* MISO0 ----4||||     */
  /* MOSI0 ---5|||||     */
  /* SCK0 ---6||||||     */
  /* SS0 ---7|||||||     */
  /*        ||||||||     */
  /*        VVVVVVVV     */ 
  PTS  =  0b00000011;  /* Port S */
  DDRS =  0b11111110;  /* Port S (0-input / 1-output)*/ 
  
  /* Switch input */
  PTT  = 0b00000000;  /* Port T */ 
  DDRT = 0b00000000;  /* Port T (0-input / 1-output)*/ 
  
  /* PTIx Port x Input Register */
  PTIH = 0x00; /* Port H */
  PTIJ = 0x00; /* Port J */
  PTIM = 0x00; /* Port M */
  PTIP = 0x00; /* Port P */
  PTIS = 0x00; /* Port S */
  PTIT = 0x00; /* Port T */
                         
  /* RDRx Port x Reduced Drive Register (0-Full drive strength / 1-Reduced drive) */
  RDRH = 0x00;  /* Port H */                     
  RDRJ = 0x00;  /* Port J */                        
  RDRM = 0x00;  /* Port M */                       
  RDRP = 0x00;  /* Port P */                       
  RDRS = 0x00;  /* Port S */                     
  RDRT = 0x00;  /* Port T */  
  
  /* PERx Port x Pull Device Enable Register (0-Pull device disabled / 1-Pull device enabled.)*/
  PERH = 0x00; /* Port H */
  PERJ = 0b00; /* Port J */
  PERM = 0x00; /* Port M */
  PERP = 0x00; /* Port P */
  PERS = 0x00; /* Port S */
  PERT = 0xFF; /* Port T (Pull-ups for DIL Switch function) */  
  
  /* PPSx Port x Polarity Select Register (0-pull-up device / 1-pull-down device) */
  PPSH = 0x00; /* Port H */
  PPSJ = 0x00; /* Port J */
  PPSM = 0x00; /* Port M */
  PPSP = 0x00; /* Port P */
  PPSS = 0x00; /* Port S */
  PPST = 0x00; /* Port T (Pull-ups for DIL Switch function) */
  
  /* WOMx Port x Wired-Or Mode Register  */
  WOMM = 0x00; /* Port M */
  WOMS = 0x00; /* Port S */      
}


/*******************************************************************************/
/* Programmable Interrupt Timer (PIT) module registers configuration           */
/*******************************************************************************/
void PIT_Init(void)
{
  PITCFLMT_PITE = 0; 
  PITCFLMT_PITSWAI = 0;        
  PITTRIGSTAT = 128;        
  PITMTLD0 = 3;                 
  PITMTLD1 = 0;                 
  PITLD0 = 0;                  
  PITLD1 = 0;                
  PITMUX = 0;                   
  PITCE = 3;                    
  PITTF = 3;                    
  PITINTE = 0;                  
  PITCSTP = 3;                  
  PITTRIGE = 0;                 
  PITTRIGOUT = 0;               
  PITTRIGCTL = 0;               
  PITCFLMT_PITE = 1;              
}


/*******************************************************************************/
/* Software reset of MCU (Setting watchdog and waiting for overflow)           */
/*******************************************************************************/
void SPI_Init(void) 
{
  SPI1CR1 = 4;   /* Reset the device register */
  
  /* Cler Interrupt flags */
  (void)SPI1SR;  /* Read the status register */
  (void)SPI1DR;  /* Read the device register */
  
  /* Set the baud rate register */
  // BaudRateDivisor = (SPPR+1)*2^(SPR+1)
  // BaudRateDivisor = (4+1)*2^(2+1) = 5*8 = 40  
  // BaudRate = 40MHz/BaudRateDivisor = 40/40 = 1MHz
  SPI1BR_SPPR = 4;
  SPI1BR_SPR = 2;
  
  /* Set control register 2 */
  SPI1CR2_XFRW = 1; // 16-bit width
  SPI1CR2_MODFEN = 0; // SS pin is not used
  SPI1CR2_BIDIROE = 0; // Output buffer disabled
  SPI1CR2_SPISWAI = 0; // Operate normally in Wait mode
  SPI1CR2_SPC0 = 0;    // MISO is master in
 
  /* Set control register 1 */
  SPI1CR1_SPIE=0;   // SPI IRQ enabled
  SPI1CR1_SPE=1;    // SPI Enabled
  SPI1CR1_SPTIE=0;  // Transmit interrupt dissabled
  SPI1CR1_MSTR=1;   // SPI in Master mode
  SPI1CR1_CPOL=0;   // Active-High clock (CLK=0 in Idle state)
  SPI1CR1_CPHA=1;   // Sampling of data on even edges (2.4.6) -> falling edges
  SPI1CR1_SSOE=0;   // SS disable
  SPI1CR1_LSBFE=1;  // LSB first
}


/*******************************************************************************/
/* Software reset of MCU (Setting watchdog and waiting for overflow)           */
/*******************************************************************************/
void MCU_Software_Reset(void){
  // Set watchdog but do not set watchdog reset commands
  COPCTL = 0b00000001; 
}

/*******************************************************************************/
/* Pulse Width Modulator with Fault Protection (PMF) module configuration      */
/*******************************************************************************/
void PMF_Init(void)
{
  /* PMFENCA: PWMENA=0,??=0,??=0,??=0,??=0,??=0,LDOKA=0,PWMRIEA=0 */
  PMFENCA = 0x00;
  PMFENCB = 0x00;
  PMFENCC = 0x00; 
                                    
  /* PMFFSTA: ??=0,FFLAG3=1,??=0,FFLAG2=1,??=0,FFLAG1=1,??=0,FFLAG0=1 */
  PMFFSTA = 85;                  
  
  /* Clear PWMRFx flag */
  PMFFQCA_PWMRFA = 1;
  PMFFQCB_PWMRFB = 1;
  PMFFQCC_PWMRFC = 1;              
  
  /* PMF Value 0 Register */
  /* PMFVAL0-5: PMFVAL0-5 = 0 */
  PMFVAL0 = 0x0FFF;
  PMFVAL1 = 0x0FFF;
  PMFVAL2 = 0;
  PMFVAL3 = 0;
  PMFVAL4 = 0;
  PMFVAL5 = 0;                 
                 
  /* PMF Frequency Control A Register */
  /* PMFFQCA: LDFQA=0,HALFA=0,PRSCA=3,PWMRFA=0 */
  PMFFQCA_PRSCA = 3;
  PMFFQCB_PRSCB = 3;
  PMFFQCC_PRSCC = 3;
  
  /* PMF Counter Modulo A Register */                  
  /* PMFMODA: ??=0,PMFMODA=0 */
  PMFMODA = 0x7FFF;
  PMFMODB = 100;
  PMFMODC = 100;  
  
  /* PMF Deadtime A Register */
  /* PMFDTMA: ??=0,??=0,??=0,??=0,PMFDTMA=4095 */
  PMFDTMA = 0; 
  PMFDTMB = 0; 
  PMFDTMC = 0;                
 
  /* PMF Enable Control A Register */
  /* PMFENCA: LDOKA=0 */
  PMFENCA_LDOKA = 0;                                               
  PMFENCA_LDOKA = 1;
                
  /* PMF Configure 0 Register */   
  PMFCFG0_MTG = 1;  // 1 - Multiple timebase generator.
  /* Edge-Aligned or Center-Aligned PWM */
  PMFCFG0_EDGEA = 1; // 1 - Edge-Aligned PWM for Pair A
  PMFCFG0_EDGEB = 1; // 1 - Edge-Aligned PWM for Pair B
  PMFCFG0_EDGEC = 1; // 1 - Edge-Aligned PWM for Pair C
  /* Independent or Complimentary Operation */
  PMFCFG0_INDEPA = 1; // 1 - Independent Operation for Pair A
  PMFCFG0_INDEPB = 1; // 1 - Independent Operation for Pair B
  PMFCFG0_INDEPC = 1; // 1 - Independent Operation for Pair C
  
  /* PMFCFG1: ENHA=0,??=0,BOTNEGC=0,TOPNEGC=0,BOTNEGB=0,TOPNEGB=0,BOTNEGA=0,TOPNEGA=0 */
  PMFCFG1 = 0;                  
  /* PMFCFG2: ??=0,??=0,MSK5=0,MSK4=0,MSK3=0,MSK2=0,MSK1=0,MSK0=0 */
  PMFCFG2 = 0;                  
  /* PMFCFG3: PMFWAI=0,PMFFRZ=0,??=0,VLMODE1=0,VLMODE0=0,SWAPC=0,SWAPB=0,SWAPA=0 */
  PMFCFG3 = 0;
  PMFCFG3_PMFWAI = 0; // 0 PMF continues to run in WAIT mode.                  
  
  /* PMFFCTL: FMODE3=0,FIE3=0,FMODE2=0,FIE2=0,FMODE1=0,FIE1=0,FMODE0=0,FIE0=0 */
  PMFFCTL = 0;                  
  /* PMFFPIN: ??=0,FPINE3=0,??=0,FPINE2=0,??=0,FPINE1=0,??=0,FPINE0=0 */
  PMFFPIN = 0;                  
  /* PMFQSMP: QSMP3=0,QSMP2=0,QSMP1=0,QSMP0=0 */
  PMFQSMP = 0;                  
  
  /* PMF Output Control Register */
  /* These bits enable software control of their corresponding PWM pin. */ 
  /* When OUTCTLx is set,the OUTx bit activates and deactivates the PWMx output */
  PMFOUTC_OUTCTL0 = 0;  
  PMFOUTC_OUTCTL1 = 0; 
  PMFOUTC_OUTCTL2 = 0; 
  PMFOUTC_OUTCTL3 = 0;
  PMFOUTC_OUTCTL4 = 0; // 0 Software control disabled
  PMFOUTC_OUTCTL5 = 0; // 1 Software control enabled
  
  /* PMF Output Control Bit Register */
  /* When the corresponding OUTCTL bit is set, these bits control the PWM pins */                
  PMFOUTB_OUT0 = 0; 
  PMFOUTB_OUT1 = 0;   
  PMFOUTB_OUT2 = 0;   
  PMFOUTB_OUT3 = 0;   
  PMFOUTB_OUT4 = 0; // 0 PWM1 is inactive   
  PMFOUTB_OUT5 = 0; // 1 PWM0 is active     
                 
  /* PMF Correction Control Register */
  /* PMFCCTL: ??=0,??=0,ISENS1=0,ISENS0=0,??=0,IPOLC=0,IPOLB=0,IPOLA=0 */
  PMFCCTL = 0;                  
  
  /* PMF Disable Mapping Registers */
  /* PMFDMPA: DMP13=0,DMP12=0,DMP11=0,DMP10=0,DMP03=0,DMP02=0,DMP01=0,DMP00=0 */
  /* PMFDMPB: DMP33=0,DMP32=0,DMP31=0,DMP30=0,DMP23=0,DMP22=0,DMP21=0,DMP20=0 */
  /* PMFDMPC: DMP53=0,DMP52=0,DMP51=0,DMP50=0,DMP43=0,DMP42=0,DMP41=0,DMP40=0 */
  PMFDMPA = 0; 
  PMFDMPB = 0;
  PMFDMPC = 0;                 
  
  /* Enable PWM Channel A (pins PP0 and PP1) */
  PMFENCA_PWMENA = 1;  
  
  /* PMF Configure 0 Register */             
  /* PMFCFG0: WP=0 */
  PMFCFG0_WP = 0; 
}


/*******************************************************************************/
/* Interrupts configuration                                                    */
/*******************************************************************************/
void Interrupts_Init(void)
{
    /* Access to configuration data registers for interrupts */ 
    INT_CFADDR = 0xF0;  /* Vectors from 0xFFF0 to 0xFFF8 */  
    INT_CFDATA0 = 0x06; /* Real Time Interrupt, priority 6 */    
    
    INT_CFADDR = 0xE0;  /* Vectors from 0xFFE0 to 0xFFE8 */
    INT_CFDATA0 = 0x84; /* Input Capture channel 7 assigned to XGATE, priority 4 */
    
    INT_CFADDR = 0x70;  /* Vectors from 0xFF70 to 0xFF78 */
    INT_CFDATA1 = 0x84; /* Software trigger 0 for XGATE, priority 4 */
        
    TIOS_IOS7 = 0;      /* Channel 7 configured as input capture */    
    TCTL3_EDG7B = 1;    /* Channel 7 input capture enabled in falling edges */    
    TCTL3_EDG7A = 0;                             
    
    ICSYS = 0;          /* Input capture channels in normal mode */
    PACTL = 0;          /* Pulse acumulator disabled */                                      
                                
    RTICTL_RTDEC = 1;   /* Real time interrupt decimal divider */                                                                      
    RTICTL_RTR = 0x55;  /* Divider = 300x10^3; RTI period=300k/8MHz = 37.5 ms */  
                        
    TSCR2 = 4;          /* Set timer prescaler to 16 */
  
    TFLG1_C7F = 1;      /* Clear input capture 7 interrupt request flag */
    TIE_C7I = 1;        /* Interrupt enabled for Timer channel 7 */
    
    STOP_ENABLE();      /* Enable STOP intruction */
        
    /* External IRQ Settings */
    IRQCR_IRQE = 1;     /* External IRQ responds only to falling edges */
    IRQCR_IRQEN = 1;    /* External IRQ is enabled */ 
    XIRQ_ENABLE();      /* Enable XIRQ */  
    
    CRGFLG_RTIF = 1;    /* Clear real time interrupt flag */    
    CRGINT_RTIE = 1;    /* Enable real time interrupt */    
    TSCR1_TEN = 1;      /* Timer enable */
}

/*******************************************************************************/


