(NETLIST)
(FOR DRAWING: F:/RTC010/WORK/BRD/RTC010.BRD)
(GENERATED BY: ALLEGRO 16.5 P003 (v16-5-13C))
(Fri Aug 01 16:28:06 2014)
$PACKAGES
BERG_2X2_2P54 ! 'TEST POINTS, 4 THRU-HOLE PADS_B' ,
        ! '4 Round Pads, .060 with .040 Hole' ; PR1 PR2 PR3 PR4 PR5 PR6 
C0402 ! CAP_100NF_10V_0402_C0402_100NF ! 100nF ; C39 C41 C46 C47 C48 C49 ,
        C50 C51 C52 C53 C54 C56 C57 C58 C60 C62 C65 C69 
C0402 ! CAP_10NF_16V_0402_C0402_10NF ! 10nF ; C63 
C0402 ! CAP_10PF_50V_0402_C0402_10PF ! 10pF ; C64 C66 
C0402 ! CAP_1UF_10V_0402_C0402_1UF ! 1uF ; C38 C40 C67 C68 
C0402 ! 'CAP_2PF_50V_0402_C0402_2.0PF' ! '2.0pF' ; C1 C2 C3 C4 C5 C6 C7 C8 ,
        C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 ,
        C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C37 C42 C43 
C0402 ! 'CAP_4.7UF_6.3V_0402_C0402_4.7UF' ! '4.7uF' ; C55 C59 C61 
C0603 ! CAP_10UF_10V_0603_C0603_10UF_20 ! 10uF ! '20%' ; C45 
C1206 ! CAP_10UF_10V_TANT_3216_C1206_10 ! 10uF ; C36 C44 
'CON_571-0500' ! 'BANANA JACK, THRU-HOLE, BLACK_C' ,
        ! 'Banana Jack, Thru-Hole, Black' ; J26 
'CON_571-0500' ! 'BANANA JACK, THRU-HOLE, RED_CON' ,
        ! 'Banana Jack, Thru-Hole, Red' ; J24 
'CON_571-0500' ! 'BANANA JACK, THRU-HOLE, YELLOW_' ,
        ! 'Banana Jack, Thru-Hole, Yellow' ; J25 
CON_USB_B_RA ! 'CONN, USB-B, SMT_CON_USB_B_RA_C' ! 'Conn, USB-B, SMT' ; J29 
'CRY-4P-SMD1' ! 'CRYSTAL 12 MHZ_CRY-4P-SMD1_12 M' ! '12 MHz' ; Y1 
HDR_1X2_2P54 ! 'HEADER 2-PIN 0.1_HDR_1X2_2P54_H' ! 'Header 2-pin' ; J27 J28 
HDR_1X3_2P54 ! 'HEADER 3-PIN 0.1_HDR_1X3_2P54_H' ! 'Header 3-pin' ; J5 J8 ,
        J9 J12 J16 J18 J19 J21 J23 
L0402 ! 'FERRITE BEAD, 600 OHM, 0402_L04' ! 600 ; FB3 FB4 
L0603 ! 'FERRITE BEAD, 600 OHM, 0603_L06' ! 600 ; FB1 FB2 
LED_0603 ! 'LED_GREEN_0603_LED_0603_LED, GR' ! 'LED, Green' ; LED1 
QFN_64_0P5 ! 'FT2232H DUAL USB INTERFACE_2_QF' ! FT2232H ; U2 
QFN_72P_0P5MM ! 'TMP_2_QFN_72P_0P5MM_DNI NB3N190' ! 'DNI NB3N1900K' ; U1 
R0201 ! 'SOLDER GAP_0_R0201_SOLDER GAP' ! 'Solder Gap' ; SG1 SG2 SG3 SG4 ,
        SG5 SG6 SG7 SG8 SG9 SG10 SG11 SG12 
R0402 ! 'RES_0_0201_R0402_0_5%' ! 0 ! '5%' ; R100 R102 
R0402 ! RES_0_0402_R0402_0 ! 0 ; R9 R12 R13 R15 R46 R49 R56 R59 R70 R73 R80 ,
        R84 
R0402 ! 'RES_10K_0402_R0402_10K_5%' ! 10K ! '5%' ; R104 R105 R106 R108 R109 ,
        R110 
R0402 ! 'RES_12K_1%_0402_R0402_12K_1%' ! 12K ! '1%' ; R107 
R0402 ! 'RES_2.2K_0402_R0402_2.2K_5%' ! '2.2K' ! '5%' ; R112 
R0402 ! 'RES_27_0402_R0402_33_5%' ! 33 ! '5%' ; R1 R2 R5 R6 R10 R11 R14 R18 ,
        R19 R22 R25 R27 R30 R31 R32 R34 R37 R39 R41 R43 R45 R48 R51 R53 R55 ,
        R58 R61 R65 R69 R72 R75 R77 R79 R83 R88 R92 R95 R97 
R0402 ! 'RES_42.2_0402_R0402_49.9_1%' ! '49.9' ! '1%' ; R3 R4 R7 R8 R16 R17 ,
        R20 R21 R23 R24 R26 R28 R29 R33 R35 R36 R38 R40 R42 R44 R47 R50 R52 ,
        R54 R57 R60 R62 R66 R71 R74 R76 R78 R82 R87 R90 R94 R96 R98 
R0402 ! 'RES_470_0402_R0402_470_5%' ! 470 ! '5%' ; R111 
R0402 ! 'RES_475_1%_0402_R0402_475_1%' ! 475 ! '1%' ; R99 
R0402 ! 'RES_82.5_1%_0402_R0402_82.5_1%' ! '82.5' ! '1%' ; R101 R103 
R0603 ! 'RES_2.2_0603_R0603_2.2_5%' ! '2.2' ! '5%' ; R91 R93 
R0603 ! 'RES_4.7K_0603_R0603_4.7K_5%' ! '4.7K' ! '5%' ; R67 R68 R85 R89 
R0603 ! 'RES_4.7K_0603_R0603_DNI 4.7K_5%' ! 'DNI 4.7K' ! '5%' ; R81 R86 
R0603 ! 'RES_49.9_0603_R0603_49.9_1%' ! '49.9' ! '1%' ; R63 R64 
SMA_JACK_END_LAUNCH ! 'SMA JACK, END LAUNCH_0_SMA_JACK' ,
        ! 'SMA Jack, End Launch' ; J1 J2 J3 J4 J6 J7 J10 J11 J13 J14 J15 ,
        J17 J20 J22 
SOT23_5P ! 'NCP 4586 3.3V REGULATOR_SOT23_5' ! 'NCP4586, 3.3V' ; U4 
SOT_143 ! 'PACDN004 2-CHAN ESD DIODE ARRAY' ! PACDN004 ; D1 
TP_30_30 ! 'TEST PAD 30 X 30 MIL_0_TP_30_30' ! 'Test Pad 30 x 30 mil' ; ,
        TP10 
TP_30_30 ! 'TEST PAD 30 X 30 MIL_1_TP_30_30' ! 'Test Pad 30 x 30 mil' ; TP1 ,
        TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP11 TP12 TP13 TP14 TP15 TP16 TP17 ,
        TP18 TP19 TP20 TP21 TP22 TP24 TP26 TP28 TP29 
TP_30_60 ! 'TEST PAD 30 X 60 MIL_0_TP_30_60' ! 'Test Pad 30 x 60 mil' ; ,
        TP35 TP36 
TP_50_100 ! 'TEST PAD 50 X 100 MIL_0_TP_50_1' ! 'Test Pad 50 x 100 mil' ; ,
        TP37 TP38 TP39 TP40 
TP_70_135 ! 'TEST POINT, KEYSTONE 5015_0_TP_' ! 'Test Point, SMT' ; TP23 ,
        TP25 TP27 TP30 TP33 TP34 
TP_70_135 ! 'TEST POINT, KEYSTONE 5015_1_TP_' ! 'Test Point, SMT' ; TP31 
TP_70_135 ! 'TEST POINT, KEYSTONE 5015_2_TP_' ! 'Test Point, SMT' ; TP32 
TSSOP_8_4P4W_0P65 ! '93LC46B SERIAL EEPROM_0_TSSOP_8' ! 93LC46B ; U3 
$NETS
3V3 ; C51.1 C52.1 C53.1 C54.1 C65.1 C68.1 FB3.2 FB4.2 R104.1 R105.1 R106.2 ,
        R108.1 R109.1 R110.1 TP36.1 U2.20 U2.31 U2.42 U2.50 U2.56 U3.6 U3.7 ,
        U3.8 U4.5 
CLKIN ; J13.1 R64.2 U1.9 
'CLKIN#' ; J14.1 R63.2 U1.10 
DIF0 ; R2.1 U1.19 
DIF1 ; R11.1 U1.22 
DIF2 ; R19.1 U1.24 
DIF3 ; R32.1 U1.27 
DIF4 ; R37.1 U1.29 
DIF5 ; R41.1 U1.32 
DIF6 ; R45.1 U1.35 
DIF7 ; R51.1 U1.38 
DIF8 ; R55.1 U1.41 
DIF9 ; R61.1 U1.46 
DIF10 ; R69.1 U1.49 
DIF11 ; R75.1 U1.52 
DIF12 ; R79.1 U1.55 
DIF13 ; R88.1 U1.59 
DIF14 ; R95.1 U1.61 
DIF15 ; R1.2 U1.64 
DIF16 ; R10.2 U1.66 
DIF17 ; R18.2 U1.69 
DIF18 ; R25.2 U1.71 
'DIF0#' ; R6.1 U1.20 
'DIF1#' ; R14.1 U1.23 
'DIF10#' ; R72.1 U1.50 
'DIF11#' ; R77.1 U1.53 
'DIF12#' ; R83.1 U1.56 
'DIF13#' ; R92.1 U1.60 
'DIF14#' ; R97.1 U1.62 
'DIF15#' ; R5.2 U1.65 
'DIF16#' ; R30.2 U1.67 
'DIF17#' ; R22.2 U1.70 
'DIF18#' ; R27.2 U1.72 
'DIF2#' ; R31.1 U1.25 
'DIF3#' ; R34.1 U1.28 
'DIF4#' ; R39.1 U1.30 
'DIF5#' ; R43.1 U1.33 
'DIF6#' ; R48.1 U1.36 
'DIF7#' ; R53.1 U1.39 
'DIF8#' ; R58.1 U1.42 
'DIF9#' ; R65.1 U1.47 
GND ; C1.1 C2.2 C3.1 C4.2 C5.1 C6.2 C7.1 C8.2 C9.2 C10.1 C11.2 C12.1 C13.2 ,
        C14.1 C15.1 C16.2 C17.2 C18.2 C19.2 C20.2 C21.2 C22.2 C23.2 C24.2 ,
        C25.2 C26.2 C27.2 C28.2 C29.2 C30.2 C31.2 C32.2 C33.2 C34.2 C35.2 ,
        C36.2 C37.2 C38.2 C39.2 C40.2 C41.2 C42.2 C43.2 C44.2 C45.2 C46.2 ,
        C47.2 C48.2 C49.2 C50.2 C51.2 C52.2 C53.2 C54.2 C55.2 C56.2 C57.2 ,
        C58.2 C59.2 C60.2 C61.2 C62.2 C63.2 C64.2 C65.2 C66.2 C67.2 C68.2 ,
        C69.2 D1.1 J1.2 J1.3 J1.4 J1.5 J2.2 J2.3 J2.4 J2.5 J3.2 J3.3 J3.4 ,
        J3.5 J4.2 J4.3 J4.4 J4.5 J5.3 J6.2 J6.3 J6.4 J6.5 J7.2 J7.3 J7.4 ,
        J7.5 J8.3 J9.3 J10.2 J10.3 J10.4 J10.5 J11.2 J11.3 J11.4 J11.5 ,
        J12.3 J13.2 J13.3 J13.4 J13.5 J14.2 J14.3 J14.4 J14.5 J15.2 J15.3 ,
        J15.4 J15.5 J16.3 J17.2 J17.3 J17.4 J17.5 J18.3 J19.3 J20.2 J20.3 ,
        J20.4 J20.5 J21.3 J22.2 J22.3 J22.4 J22.5 J23.3 J26.1 J26.2 J29.4 ,
        J29.5 J29.6 LED1.2 PR1.3 PR1.4 PR2.3 PR2.4 PR3.3 PR3.4 PR4.3 PR4.4 ,
        PR5.3 PR5.4 PR6.3 PR6.4 R3.1 R4.2 R7.1 R8.2 R16.1 R17.2 R20.1 R21.2 ,
        R23.1 R24.2 R26.2 R28.1 R29.2 R33.1 R35.1 R36.2 R38.2 R40.2 R42.2 ,
        R44.2 R47.2 R50.2 R52.2 R54.2 R57.2 R60.2 R62.2 R63.1 R64.1 R66.2 ,
        R68.2 R71.2 R74.2 R76.2 R78.2 R82.2 R85.2 R87.2 R89.2 R90.2 R94.2 ,
        R96.2 R98.2 R99.2 R101.2 R103.2 R107.2 TP37.1 TP38.1 TP39.1 TP40.1 ,
        U1.2 U1.7 U1.26 U1.44 U1.63 U1.73 U2.1 U2.5 U2.10 U2.11 U2.13 U2.15 ,
        U2.25 U2.35 U2.47 U2.51 U3.5 U4.2 Y1.2 Y1.4 
N07511 ; FB1.2 R91.1 R93.1 
N14576354 ; J18.2 U1.4 
N14576507 ; J19.2 U1.6 
N14576736 ; J16.2 R67.2 R68.1 U1.5 
N16357698 ; LED1.1 R111.2 
N16367612 ; J28.1 R105.2 U2.17 U2.18 
N16423312 ; C44.1 FB2.1 J25.1 J25.2 
N16475854 ; J27.1 R104.2 U2.16 
N16706504 ; C64.1 U2.2 Y1.1 
N16706508 ; C66.1 U2.3 Y1.3 
N16706706 ; C59.1 C60.1 FB3.1 U2.9 
N16706738 ; C61.1 C62.1 FB4.1 U2.4 
N16707304 ; R112.2 U2.61 U3.3 
N16707308 ; R110.2 R112.1 U3.4 
N16707312 ; R108.2 U2.63 U3.1 
N16707410 ; R107.1 U2.6 
N16707506 ; C55.1 C56.1 C57.1 C58.1 U2.12 U2.37 U2.49 U2.64 
N16708128 ; R109.2 U2.62 U3.2 
N16798453 ; J2.1 R12.2 
N16798477 ; PR2.2 SG4.2 
N16798521 ; J4.1 R15.2 
N16799042 ; J6.1 R46.2 
N16799108 ; J7.1 R49.2 
N16799312 ; J10.1 R56.2 
N16799367 ; J11.1 R59.2 
N16799535 ; J15.1 R70.2 
N16799608 ; J17.1 R73.2 
N16799632 ; PR2.1 SG2.2 
N16800265 ; PR3.2 SG6.2 
N16800969 ; PR4.2 SG8.2 
N16801662 ; PR3.1 SG5.2 
N16801902 ; PR5.2 SG10.2 
N16802115 ; PR4.1 SG7.2 
N16802449 ; PR5.1 SG9.2 
N16985096 ; PR6.2 SG12.2 
N16985413 ; PR6.1 SG11.2 
N16985829 ; J20.1 R80.2 
N16985840 ; J22.1 R84.2 
N17056832 ; J1.1 R9.1 
N17056842 ; PR1.1 SG1.1 
N17056960 ; J3.1 R13.1 
N17056962 ; PR1.2 SG3.1 
N17635870 ; R100.2 TP31.1 
N17635874 ; R102.2 TP32.1 
N17635890 ; R99.1 U1.3 
N17635892 ; R102.1 R103.1 U1.18 
N17635894 ; R100.1 R101.1 U1.17 
OE_IO5 ; U1.34 U2.21 
OE_IO6 ; J5.2 U1.37 U2.22 
OE_IO7 ; U1.40 U2.23 
OE_IO8 ; J8.2 U1.43 U2.24 
OE_IO9 ; U1.48 U2.26 
OE_IO10 ; J9.2 U1.51 U2.27 
OE_IO11 ; U1.54 U2.28 
OE_IO12 ; J12.2 U1.57 U2.29 
OUT0 ; C2.1 R2.2 R4.1 TP2.1 
OUT1 ; C6.1 R11.2 R12.1 R29.1 SG2.1 
OUT2 ; C9.1 R19.2 R21.1 TP11.1 
OUT3 ; C13.1 R26.1 R32.2 TP9.1 
OUT4 ; C17.1 R37.2 R38.1 TP13.1 
OUT5 ; C19.1 R41.2 R42.1 TP15.1 
OUT6 ; C21.1 R45.2 R46.1 R47.1 SG5.1 
OUT7 ; C23.1 R51.2 R52.1 TP17.1 
OUT8 ; C25.1 R55.2 R56.1 R57.1 SG7.1 
OUT9 ; C27.1 R61.2 R62.1 TP19.1 
OUT10 ; C29.1 R69.2 R70.1 R71.1 SG9.1 
OUT11 ; C31.1 R75.2 R76.1 TP21.1 
OUT12 ; C33.1 R79.2 R80.1 R82.1 SG11.1 
OUT13 ; C35.1 R88.2 R90.1 TP24.1 
OUT14 ; C42.1 R95.2 R96.1 TP28.1 
OUT16 ; C5.2 R9.2 R10.1 R28.2 SG1.2 
'OUT0#' ; C4.1 R6.2 R8.1 TP4.1 
'OUT1#' ; C8.1 R14.2 R15.1 R17.1 SG4.1 
'OUT10#' ; C30.1 R72.2 R73.1 R74.1 SG10.1 
'OUT11#' ; C32.1 R77.2 R78.1 TP22.1 
'OUT12#' ; C34.1 R83.2 R84.1 R87.1 SG12.1 
'OUT13#' ; C37.1 R92.2 R94.1 TP26.1 
'OUT14#' ; C43.1 R97.2 R98.1 TP29.1 
'OUT16#' ; C7.2 R13.2 R16.2 R30.1 SG3.2 
'OUT2#' ; C11.1 R24.1 R31.2 TP7.1 
'OUT3#' ; C16.1 R34.2 R36.1 TP12.1 
'OUT4#' ; C18.1 R39.2 R40.1 TP14.1 
'OUT5#' ; C20.1 R43.2 R44.1 TP16.1 
'OUT6#' ; C22.1 R48.2 R49.1 R50.1 SG6.1 
'OUT7#' ; C24.1 R53.2 R54.1 TP18.1 
'OUT8#' ; C26.1 R58.2 R59.1 R60.1 SG8.1 
'OUT9#' ; C28.1 R65.2 R66.1 TP20.1 
SA0 ; J21.2 R81.2 R85.1 U1.11 
SA1 ; J23.2 R86.2 R89.1 U1.14 
SCL ; J27.2 TP33.1 U1.13 
SDA ; J28.2 TP34.1 U1.12 
TP_DIFF15 ; C1.2 R1.1 R3.2 TP1.1 
TP_DIFF17 ; C15.2 R18.1 R20.2 TP5.1 
TP_DIFF18 ; C12.2 R25.1 R33.2 TP8.1 
'TP_DIFF15#' ; C3.2 R5.1 R7.2 TP3.1 
'TP_DIFF17#' ; C10.2 R22.1 R23.2 TP6.1 
'TP_DIFF18#' ; C14.2 R27.1 R35.2 TP10.1 
USB_5V ; C67.1 C69.1 D1.4 J29.1 R111.1 TP35.1 U4.1 U4.3 
USB_DM ; D1.3 J29.2 U2.7 
USB_DP ; D1.2 J29.3 U2.8 
'USB_RST#' ; C63.1 R106.1 U2.14 
VDD ; C36.1 FB1.1 J5.1 J8.1 J9.1 J12.1 J16.1 J18.1 J19.1 J21.1 J23.1 J24.1 ,
        J24.2 R67.1 R81.1 R86.1 TP23.1 
VDDA ; C38.1 C39.1 R91.2 TP25.1 U1.1 
VDDIO ; C45.1 C46.1 C47.1 C48.1 C49.1 C50.1 FB2.2 TP30.1 U1.21 U1.31 U1.45 ,
        U1.58 U1.68 
VDDR ; C40.1 C41.1 R93.2 TP27.1 U1.8 
$NETS
$A_PROPERTIES
LOGICAL_PATH '@rtc010.schematic1(sch_1):n17635894'; 'N17635894'
LOGICAL_PATH '@rtc010.schematic1(sch_1):n17635870'; 'N17635870'
LOGICAL_PATH '@rtc010.schematic1(sch_1):n17635890'; 'N17635890'
LOGICAL_PATH '@rtc010.schematic1(sch_1):n17635874'; 'N17635874'
LOGICAL_PATH '@rtc010.schematic1(sch_1):n14576736'; 'N14576736'
LOGICAL_PATH '@rtc010.schematic1(sch_1):tp_diff17'; 'TP_DIFF17'
LOGICAL_PATH '@rtc010.schematic1(sch_1):\tp_diff17#\'; 'TP_DIFF17#'
LOGICAL_PATH '@rtc010.schematic1(sch_1):tp_diff15'; 'TP_DIFF15'
LOGICAL_PATH '@rtc010.schematic1(sch_1):oe_io12'; 'OE_IO12'
LOGICAL_PATH '@rtc010.schematic1(sch_1):oe_io11'; 'OE_IO11'
LOGICAL_PATH '@rtc010.schematic1(sch_1):oe_io10'; 'OE_IO10'
LOGICAL_PATH '@rtc010.schematic1(sch_1):oe_io9'; 'OE_IO9'
LOGICAL_PATH '@rtc010.schematic1(sch_1):oe_io8'; 'OE_IO8'
LOGICAL_PATH '@rtc010.schematic1(sch_1):oe_io5'; 'OE_IO5'
LOGICAL_PATH '@rtc010.schematic1(sch_1):oe_io6'; 'OE_IO6'
LOGICAL_PATH '@rtc010.schematic1(sch_1):oe_io7'; 'OE_IO7'
LOGICAL_PATH '@rtc010.schematic1(sch_1):vddio'; 'VDDIO'
LOGICAL_PATH '@rtc010.schematic1(sch_1):\out16#\'; 'OUT16#'
LOGICAL_PATH '@rtc010.schematic1(sch_1):\out12#\'; 'OUT12#'
LOGICAL_PATH '@rtc010.schematic1(sch_1):\3v3\'; '3V3'
LOGICAL_PATH '@rtc010.schematic1(sch_1):\out8#\'; 'OUT8#'
LOGICAL_PATH '@rtc010.schematic1(sch_1):\out6#\'; 'OUT6#'
LOGICAL_PATH '@rtc010.schematic1(sch_1):\out1#\'; 'OUT1#'
LOGICAL_PATH '@rtc010.schematic1(sch_1):out16'; 'OUT16'
LOGICAL_PATH '@rtc010.schematic1(sch_1):clkin'; 'CLKIN'
LOGICAL_PATH '@rtc010.schematic1(sch_1):\clkin#\'; 'CLKIN#'
LOGICAL_PATH '@rtc010.schematic1(sch_1):\dif18#\'; 'DIF18#'
LOGICAL_PATH '@rtc010.schematic1(sch_1):\dif17#\'; 'DIF17#'
LOGICAL_PATH '@rtc010.schematic1(sch_1):vdda'; 'VDDA'
LOGICAL_PATH '@rtc010.schematic1(sch_1):\dif15#\'; 'DIF15#'
LOGICAL_PATH '@rtc010.schematic1(sch_1):\dif14#\'; 'DIF14#'
LOGICAL_PATH '@rtc010.schematic1(sch_1):\dif13#\'; 'DIF13#'
LOGICAL_PATH '@rtc010.schematic1(sch_1):n14576507'; 'N14576507'
LOGICAL_PATH '@rtc010.schematic1(sch_1):n16802115'; 'N16802115'
LOGICAL_PATH '@rtc010.schematic1(sch_1):n16801662'; 'N16801662'
LOGICAL_PATH '@rtc010.schematic1(sch_1):n16798521'; 'N16798521'
LOGICAL_PATH '@rtc010.schematic1(sch_1):n16800969'; 'N16800969'
LOGICAL_PATH '@rtc010.schematic1(sch_1):n16707506'; 'N16707506'
SPACING_CONSTRAINT_SET 'PWR'; 'N16707506'
PHYSICAL_CONSTRAINT_SET 'PWR'; 'N16707506'
LOGICAL_PATH '@rtc010.schematic1(sch_1):n16706504'; 'N16706504'
LOGICAL_PATH '@rtc010.schematic1(sch_1):n16798453'; 'N16798453'
LOGICAL_PATH '@rtc010.schematic1(sch_1):n16708128'; 'N16708128'
LOGICAL_PATH '@rtc010.schematic1(sch_1):n16706738'; 'N16706738'
LOGICAL_PATH '@rtc010.schematic1(sch_1):n16707410'; 'N16707410'
LOGICAL_PATH '@rtc010.schematic1(sch_1):n16706706'; 'N16706706'
LOGICAL_PATH '@rtc010.schematic1(sch_1):n16707304'; 'N16707304'
LOGICAL_PATH '@rtc010.schematic1(sch_1):n16706508'; 'N16706508'
LOGICAL_PATH '@rtc010.schematic1(sch_1):n16802449'; 'N16802449'
LOGICAL_PATH '@rtc010.schematic1(sch_1):n16707312'; 'N16707312'
LOGICAL_PATH '@rtc010.schematic1(sch_1):n16707308'; 'N16707308'
LOGICAL_PATH '@rtc010.schematic1(sch_1):gnd'; 'GND'
SAME_NET_SPACING_CONSTRAINT_SET 'GND'; 'GND'
LOGICAL_PATH '@rtc010.schematic1(sch_1):n16423312'; 'N16423312'
LOGICAL_PATH '@rtc010.schematic1(sch_1):n16799632'; 'N16799632'
LOGICAL_PATH '@rtc010.schematic1(sch_1):n16799108'; 'N16799108'
LOGICAL_PATH '@rtc010.schematic1(sch_1):n16801902'; 'N16801902'
LOGICAL_PATH '@rtc010.schematic1(sch_1):n16798477'; 'N16798477'
LOGICAL_PATH '@rtc010.schematic1(sch_1):n16799367'; 'N16799367'
LOGICAL_PATH '@rtc010.schematic1(sch_1):n16799312'; 'N16799312'
LOGICAL_PATH '@rtc010.schematic1(sch_1):n16799042'; 'N16799042'
LOGICAL_PATH '@rtc010.schematic1(sch_1):n16800265'; 'N16800265'
LOGICAL_PATH '@rtc010.schematic1(sch_1):n16799608'; 'N16799608'
LOGICAL_PATH '@rtc010.schematic1(sch_1):n16799535'; 'N16799535'
LOGICAL_PATH '@rtc010.schematic1(sch_1):n07511'; 'N07511'
LOGICAL_PATH '@rtc010.schematic1(sch_1):n16367612'; 'N16367612'
LOGICAL_PATH '@rtc010.schematic1(sch_1):vdd'; 'VDD'
SAME_NET_SPACING_CONSTRAINT_SET 'PWR'; 'VDD' 'USB_5V' 'VDDA' 'VDDR' '3V3' 'VDDIO'
MIN_LINE_WIDTH '5.7 MIL'; 'DIF13' 'DIF13#'
SPACING_CONSTRAINT_SET 'DIFF_100E'; 'DIF12' 'DIF13' 'DIF14' 'OUT12' 'DIF15' 'DIF16',
           'DIF17' 'DIF18' 'DIF7' 'DIF8' 'DIF9' 'DIF10',
           'DIF11' 'DIF0' 'OUT1' 'DIF1' 'DIF2' 'DIF3',
           'DIF4' 'DIF1#' 'DIF5' 'OUT6' 'DIF6' 'OUT8',
           'OUT10' 'DIF2#' 'DIF3#' 'DIF4#' 'DIF5#' 'DIF6#',
           'DIF7#' 'DIF8#' 'DIF9#' 'DIF10#' 'DIF11#' 'DIF12#',
           'DIF13#' 'DIF14#' 'DIF15#' 'DIF16#' 'DIF17#' 'DIF18#',
           'CLKIN#' 'CLKIN' 'OUT16' 'OUT1#' 'OUT6#' 'OUT8#',
           'OUT10#' 'OUT12#' 'OUT16#' 'DIF0#' 'TP_DIFF15' 'TP_DIFF15#',
           'TP_DIFF17#' 'TP_DIFF18#' 'TP_DIFF17' 'TP_DIFF18' 'N17635894' 'N17635892',
           'OUT0' 'OUT0#' 'OUT2' 'OUT2#' 'OUT3' 'OUT3#',
           'OUT4' 'OUT4#' 'OUT5' 'OUT5#' 'OUT7' 'OUT7#',
           'OUT9' 'OUT9#' 'OUT11' 'OUT11#' 'OUT13' 'OUT13#',
           'OUT14' 'OUT14#'
LOGICAL_PATH '@rtc010.schematic1(sch_1):dif12'; 'DIF12'
PHYSICAL_CONSTRAINT_SET 'DIFF_100E'; 'DIF12' 'DIF13' 'DIF14' 'OUT12' 'DIF15' 'DIF16',
           'DIF17' 'DIF18' 'DIF7' 'DIF8' 'DIF9' 'DIF10',
           'DIF11' 'DIF0' 'OUT1' 'DIF1' 'DIF2' 'DIF3',
           'DIF4' 'DIF1#' 'DIF5' 'OUT6' 'DIF6' 'OUT8',
           'OUT10' 'DIF2#' 'DIF3#' 'DIF4#' 'DIF5#' 'DIF6#',
           'DIF7#' 'DIF8#' 'DIF9#' 'DIF10#' 'DIF11#' 'DIF12#',
           'DIF13#' 'DIF14#' 'DIF15#' 'DIF16#' 'DIF17#' 'DIF18#',
           'CLKIN#' 'CLKIN' 'OUT16' 'OUT1#' 'OUT6#' 'OUT8#',
           'OUT10#' 'OUT12#' 'OUT16#' 'DIF0#' 'TP_DIFF15' 'TP_DIFF15#',
           'TP_DIFF17#' 'TP_DIFF18#' 'TP_DIFF17' 'TP_DIFF18' 'N17635894' 'N17635892',
           'OUT0' 'OUT0#' 'OUT2' 'OUT2#' 'OUT3' 'OUT3#',
           'OUT4' 'OUT4#' 'OUT5' 'OUT5#' 'OUT7' 'OUT7#',
           'OUT9' 'OUT9#' 'OUT11' 'OUT11#' 'OUT13' 'OUT13#',
           'OUT14' 'OUT14#'
SAME_NET_SPACING_CONSTRAINT_SET 'DIFF_100E'; 'DIF12' 'DIF13' 'DIF14' 'OUT12' 'DIF15' 'DIF16',
           'DIF17' 'DIF18' 'DIF7' 'DIF8' 'DIF9' 'DIF10',
           'DIF11' 'DIF0' 'OUT1' 'DIF1' 'DIF2' 'DIF3',
           'DIF4' 'DIF1#' 'DIF5' 'OUT6' 'DIF6' 'OUT8',
           'OUT10' 'DIF2#' 'DIF3#' 'DIF4#' 'DIF5#' 'DIF6#',
           'DIF7#' 'DIF8#' 'DIF9#' 'DIF10#' 'DIF11#' 'DIF12#',
           'DIF13#' 'DIF14#' 'DIF15#' 'DIF16#' 'DIF17#' 'DIF18#',
           'CLKIN#' 'CLKIN' 'OUT16' 'OUT1#' 'OUT6#' 'OUT8#',
           'OUT10#' 'OUT12#' 'OUT16#' 'DIF0#' 'TP_DIFF15' 'TP_DIFF15#',
           'TP_DIFF17#' 'TP_DIFF18#' 'TP_DIFF17' 'TP_DIFF18' 'OUT0' 'OUT0#',
           'OUT2' 'OUT2#' 'OUT3' 'OUT3#' 'OUT4' 'OUT4#',
           'OUT5' 'OUT5#' 'OUT7' 'OUT7#' 'OUT9' 'OUT9#',
           'OUT11' 'OUT11#' 'OUT13' 'OUT13#' 'OUT14' 'OUT14#'
DIFFP_MIN_SPACE '5 MIL'; 'DIF12' 'DIF13' 'DIF14' 'OUT12' 'DIF15' 'DIF16',
           'DIF17' 'DIF18' 'DIF7' 'DIF8' 'DIF9' 'DIF10',
           'DIF11' 'DIF0' 'OUT1' 'DIF1' 'DIF2' 'DIF3',
           'DIF4' 'DIF1#' 'DIF5' 'OUT6' 'DIF6' 'OUT8',
           'OUT10' 'DIF2#' 'DIF3#' 'DIF4#' 'DIF5#' 'DIF6#',
           'DIF7#' 'DIF8#' 'DIF9#' 'DIF10#' 'DIF11#' 'DIF12#',
           'DIF13#' 'DIF14#' 'DIF15#' 'DIF16#' 'DIF17#' 'DIF18#',
           'CLKIN#' 'CLKIN' 'OUT16' 'OUT1#' 'OUT6#' 'OUT8#',
           'OUT10#' 'USB_DP' 'USB_DM' 'OUT12#' 'OUT16#' 'DIF0#',
           'TP_DIFF15' 'TP_DIFF15#' 'TP_DIFF17#' 'TP_DIFF18#' 'TP_DIFF17' 'TP_DIFF18',
           'N17635894' 'N17635892' 'OUT0' 'OUT0#' 'OUT2' 'OUT2#',
           'OUT3' 'OUT3#' 'OUT4' 'OUT4#' 'OUT5' 'OUT5#',
           'OUT7' 'OUT7#' 'OUT9' 'OUT9#' 'OUT11' 'OUT11#',
           'OUT13' 'OUT13#' 'OUT14' 'OUT14#'
LOGICAL_PATH '@rtc010.schematic1(sch_1):n16985829'; 'N16985829'
LOGICAL_PATH '@rtc010.schematic1(sch_1):n16985096'; 'N16985096'
LOGICAL_PATH '@rtc010.schematic1(sch_1):sda'; 'SDA'
LOGICAL_PATH '@rtc010.schematic1(sch_1):scl'; 'SCL'
LOGICAL_PATH '@rtc010.schematic1(sch_1):n16985840'; 'N16985840'
LOGICAL_PATH '@rtc010.schematic1(sch_1):n16985413'; 'N16985413'
DIFFERENTIAL_PAIR 'DP14'; 'OUT13' 'OUT13#'
DIFFERENTIAL_PAIR 'DP10'; 'OUT9' 'OUT9#'
DIFFERENTIAL_PAIR 'DP6'; 'OUT5' 'OUT5#'
DIFFERENTIAL_PAIR 'DP4'; 'OUT3' 'OUT3#'
DIFFERENTIAL_PAIR 'DP1'; 'OUT0' 'OUT0#'
DIFFERENTIAL_PAIR 'TP_DIFF15'; 'TP_DIFF15' 'TP_DIFF15#'
DIFFERENTIAL_PAIR 'DP40'; 'USB_DP' 'USB_DM'
DIFFERENTIAL_PAIR 'DP17'; 'OUT16' 'OUT16#'
DIFFERENTIAL_PAIR 'DP11'; 'OUT10' 'OUT10#'
DIFFERENTIAL_PAIR 'DP9'; 'OUT8' 'OUT8#'
DIFFERENTIAL_PAIR 'DP26'; 'DIF6' 'DIF6#'
DIFFERENTIAL_PAIR 'DP7'; 'OUT6' 'OUT6#'
DIFFERENTIAL_PAIR 'DP25'; 'DIF5' 'DIF5#'
DIFFERENTIAL_PAIR 'DP32'; 'DIF12' 'DIF12#'
DIFFERENTIAL_PAIR 'DP33'; 'DIF13' 'DIF13#'
DIFFERENTIAL_PAIR 'DP34'; 'DIF14' 'DIF14#'
DIFFERENTIAL_PAIR 'DP13'; 'OUT12' 'OUT12#'
DIFFERENTIAL_PAIR 'DP35'; 'DIF15' 'DIF15#'
DIFFERENTIAL_PAIR 'DP36'; 'DIF16' 'DIF16#'
DIFFERENTIAL_PAIR 'DP37'; 'DIF17' 'DIF17#'
DIFFERENTIAL_PAIR 'DP38'; 'DIF18' 'DIF18#'
DIFFERENTIAL_PAIR 'DP27'; 'DIF7' 'DIF7#'
DIFFERENTIAL_PAIR 'DP28'; 'DIF8' 'DIF8#'
DIFFERENTIAL_PAIR 'DP29'; 'DIF9' 'DIF9#'
DIFFERENTIAL_PAIR 'DP30'; 'DIF10' 'DIF10#'
DIFFERENTIAL_PAIR 'DP31'; 'DIF11' 'DIF11#'
DIFFERENTIAL_PAIR 'DP20'; 'DIF0' 'DIF0#'
DIFFERENTIAL_PAIR 'DP2'; 'OUT1' 'OUT1#'
DIFFERENTIAL_PAIR 'DP21'; 'DIF1' 'DIF1#'
DIFFERENTIAL_PAIR 'DP22'; 'DIF2' 'DIF2#'
DIFFERENTIAL_PAIR 'DP23'; 'DIF3' 'DIF3#'
DIFFERENTIAL_PAIR 'DP24'; 'DIF4' 'DIF4#'
DIFFERENTIAL_PAIR 'DP39'; 'CLKIN#' 'CLKIN'
DIFFERENTIAL_PAIR 'TP_DIFF17'; 'TP_DIFF17#' 'TP_DIFF17'
DIFFERENTIAL_PAIR 'TP_DIFF18'; 'TP_DIFF18#' 'TP_DIFF18'
DIFFERENTIAL_PAIR 'FB_OUT'; 'N17635894' 'N17635892'
DIFFERENTIAL_PAIR 'DP3'; 'OUT2' 'OUT2#'
DIFFERENTIAL_PAIR 'DP5'; 'OUT4' 'OUT4#'
DIFFERENTIAL_PAIR 'DP8'; 'OUT7' 'OUT7#'
DIFFERENTIAL_PAIR 'DP12'; 'OUT11' 'OUT11#'
DIFFERENTIAL_PAIR 'DP15'; 'OUT14' 'OUT14#'
LOGICAL_PATH '@rtc010.schematic1(sch_1):dif13'; 'DIF13'
LOGICAL_PATH '@rtc010.schematic1(sch_1):dif14'; 'DIF14'
LOGICAL_PATH '@rtc010.schematic1(sch_1):out12'; 'OUT12'
LOGICAL_PATH '@rtc010.schematic1(sch_1):dif15'; 'DIF15'
LOGICAL_PATH '@rtc010.schematic1(sch_1):dif16'; 'DIF16'
LOGICAL_PATH '@rtc010.schematic1(sch_1):dif17'; 'DIF17'
LOGICAL_PATH '@rtc010.schematic1(sch_1):dif18'; 'DIF18'
LOGICAL_PATH '@rtc010.schematic1(sch_1):dif7'; 'DIF7'
LOGICAL_PATH '@rtc010.schematic1(sch_1):dif8'; 'DIF8'
LOGICAL_PATH '@rtc010.schematic1(sch_1):dif9'; 'DIF9'
LOGICAL_PATH '@rtc010.schematic1(sch_1):dif10'; 'DIF10'
LOGICAL_PATH '@rtc010.schematic1(sch_1):dif11'; 'DIF11'
LOGICAL_PATH '@rtc010.schematic1(sch_1):dif0'; 'DIF0'
LOGICAL_PATH '@rtc010.schematic1(sch_1):out1'; 'OUT1'
LOGICAL_PATH '@rtc010.schematic1(sch_1):dif1'; 'DIF1'
LOGICAL_PATH '@rtc010.schematic1(sch_1):dif2'; 'DIF2'
LOGICAL_PATH '@rtc010.schematic1(sch_1):dif3'; 'DIF3'
LOGICAL_PATH '@rtc010.schematic1(sch_1):usb_5v'; 'USB_5V'
SAME_NET_SPACING_CONSTRAINT_SET '3W'; 'N14576354' 'N14576507'
LOGICAL_PATH '@rtc010.schematic1(sch_1):n14576354'; 'N14576354'
LOGICAL_PATH '@rtc010.schematic1(sch_1):dif4'; 'DIF4'
LOGICAL_PATH '@rtc010.schematic1(sch_1):\dif1#\'; 'DIF1#'
LOGICAL_PATH '@rtc010.schematic1(sch_1):dif5'; 'DIF5'
LOGICAL_PATH '@rtc010.schematic1(sch_1):out6'; 'OUT6'
LOGICAL_PATH '@rtc010.schematic1(sch_1):dif6'; 'DIF6'
LOGICAL_PATH '@rtc010.schematic1(sch_1):out8'; 'OUT8'
LOGICAL_PATH '@rtc010.schematic1(sch_1):out10'; 'OUT10'
LOGICAL_PATH '@rtc010.schematic1(sch_1):\dif2#\'; 'DIF2#'
LOGICAL_PATH '@rtc010.schematic1(sch_1):\dif3#\'; 'DIF3#'
LOGICAL_PATH '@rtc010.schematic1(sch_1):\dif4#\'; 'DIF4#'
LOGICAL_PATH '@rtc010.schematic1(sch_1):\dif5#\'; 'DIF5#'
LOGICAL_PATH '@rtc010.schematic1(sch_1):\dif6#\'; 'DIF6#'
LOGICAL_PATH '@rtc010.schematic1(sch_1):\dif7#\'; 'DIF7#'
LOGICAL_PATH '@rtc010.schematic1(sch_1):\dif8#\'; 'DIF8#'
LOGICAL_PATH '@rtc010.schematic1(sch_1):\dif9#\'; 'DIF9#'
LOGICAL_PATH '@rtc010.schematic1(sch_1):\dif10#\'; 'DIF10#'
LOGICAL_PATH '@rtc010.schematic1(sch_1):\dif11#\'; 'DIF11#'
LOGICAL_PATH '@rtc010.schematic1(sch_1):\dif12#\'; 'DIF12#'
LOGICAL_PATH '@rtc010.schematic1(sch_1):\dif16#\'; 'DIF16#'
LOGICAL_PATH '@rtc010.schematic1(sch_1):vddr'; 'VDDR'
LOGICAL_PATH '@rtc010.schematic1(sch_1):sa0'; 'SA0'
LOGICAL_PATH '@rtc010.schematic1(sch_1):sa1'; 'SA1'
LOGICAL_PATH '@rtc010.schematic1(sch_1):n17056832'; 'N17056832'
LOGICAL_PATH '@rtc010.schematic1(sch_1):n17056960'; 'N17056960'
LOGICAL_PATH '@rtc010.schematic1(sch_1):n17056842'; 'N17056842'
LOGICAL_PATH '@rtc010.schematic1(sch_1):n17056962'; 'N17056962'
LOGICAL_PATH '@rtc010.schematic1(sch_1):n16475854'; 'N16475854'
LOGICAL_PATH '@rtc010.schematic1(sch_1):\out10#\'; 'OUT10#'
SAME_NET_SPACING_CONSTRAINT_SET 'DIFF_90'; 'USB_DP' 'USB_DM'
LOGICAL_PATH '@rtc010.schematic1(sch_1):usb_dp'; 'USB_DP'
LOGICAL_PATH '@rtc010.schematic1(sch_1):usb_dm'; 'USB_DM'
LOGICAL_PATH '@rtc010.schematic1(sch_1):\usb_rst#\'; 'USB_RST#'
LOGICAL_PATH '@rtc010.schematic1(sch_1):n16357698'; 'N16357698'
LOGICAL_PATH '@rtc010.schematic1(sch_1):\dif0#\'; 'DIF0#'
LOGICAL_PATH '@rtc010.schematic1(sch_1):\tp_diff15#\'; 'TP_DIFF15#'
LOGICAL_PATH '@rtc010.schematic1(sch_1):\tp_diff18#\'; 'TP_DIFF18#'
LOGICAL_PATH '@rtc010.schematic1(sch_1):tp_diff18'; 'TP_DIFF18'
LOGICAL_PATH '@rtc010.schematic1(sch_1):n17635892'; 'N17635892'
LOGICAL_PATH '@rtc010.schematic1(sch_1):out0'; 'OUT0'
LOGICAL_PATH '@rtc010.schematic1(sch_1):\out0#\'; 'OUT0#'
LOGICAL_PATH '@rtc010.schematic1(sch_1):out2'; 'OUT2'
LOGICAL_PATH '@rtc010.schematic1(sch_1):\out2#\'; 'OUT2#'
LOGICAL_PATH '@rtc010.schematic1(sch_1):out3'; 'OUT3'
LOGICAL_PATH '@rtc010.schematic1(sch_1):\out3#\'; 'OUT3#'
LOGICAL_PATH '@rtc010.schematic1(sch_1):out4'; 'OUT4'
LOGICAL_PATH '@rtc010.schematic1(sch_1):\out4#\'; 'OUT4#'
LOGICAL_PATH '@rtc010.schematic1(sch_1):out5'; 'OUT5'
LOGICAL_PATH '@rtc010.schematic1(sch_1):\out5#\'; 'OUT5#'
LOGICAL_PATH '@rtc010.schematic1(sch_1):out7'; 'OUT7'
LOGICAL_PATH '@rtc010.schematic1(sch_1):\out7#\'; 'OUT7#'
LOGICAL_PATH '@rtc010.schematic1(sch_1):out9'; 'OUT9'
LOGICAL_PATH '@rtc010.schematic1(sch_1):\out9#\'; 'OUT9#'
LOGICAL_PATH '@rtc010.schematic1(sch_1):out11'; 'OUT11'
LOGICAL_PATH '@rtc010.schematic1(sch_1):\out11#\'; 'OUT11#'
LOGICAL_PATH '@rtc010.schematic1(sch_1):out13'; 'OUT13'
LOGICAL_PATH '@rtc010.schematic1(sch_1):\out13#\'; 'OUT13#'
LOGICAL_PATH '@rtc010.schematic1(sch_1):out14'; 'OUT14'
LOGICAL_PATH '@rtc010.schematic1(sch_1):\out14#\'; 'OUT14#'
$END
